{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T06:37:09Z","timestamp":1771655829127,"version":"3.50.1"},"reference-count":39,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/micro.2002.1176264","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T11:35:00Z","timestamp":1056627300000},"page":"371-382","source":"Crossref","is-referenced-by-count":23,"title":["Fetching instruction streams"],"prefix":"10.1109","author":[{"given":"A.","family":"Ramirez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"O.J.","family":"Santana","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.L.","family":"Larriba-Pey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Valero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697009"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/165939.165956"},{"key":"ref33","article-title":"Differences between the next stream predictor and the apparatus for prefetching superblocks described in us patent 6, 304,962 bl","author":"santana","year":"2002","journal-title":"Technical Report UPC-DAC-2002-18"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/12.752652"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566447"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765954"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1995.386527"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953283"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237169"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003587"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742779"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645824"},{"key":"ref12","first-page":"11","article-title":"Digital 21264 sets new standard","author":"gwennap","year":"1996","journal-title":"Microprocessor Report"},{"key":"ref13","first-page":"171","article-title":"Efficient procedure mapping using cache line coloring","author":"hashemi","year":"1997","journal-title":"Proc ACM SIGPLAN Conf Programming Language Design and Implementation"},{"key":"ref14","article-title":"The microarchitecture of the pentium 4 processor","volume":"q1","author":"hinton","year":"2001","journal-title":"Intel Technology Journal"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/74925.74953"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1997.569673"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645793"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903263"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765946"},{"key":"ref28","first-page":"10","article-title":"A stream processor fron-end","author":"ramirez","year":"2000","journal-title":"IEEE TCCA Newsletter"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195553"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2000.888343"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1994.288166"},{"key":"ref6","first-page":"17","article-title":"Spike: an optimizer for alpha\/nt executables","author":"cohn","year":"1997","journal-title":"USENIX"},{"key":"ref29","article-title":"Trace cache redundancy: Red & blue traces","author":"ramirez","year":"2000","journal-title":"Proceedings of the 6th Intl Conference on High Performance Computer Architecture"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"287","DOI":"10.1145\/223982.224439","article-title":"Next cache line and set prediction","author":"calder","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476834"},{"key":"ref7","first-page":"333","article-title":"Optimization of instruction fetch mechanisms for high issue rates","author":"conte","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155119"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645794"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/349299.349303"},{"key":"ref20","article-title":"Method and apparatus for prefetching superblocks in a computer processing system","author":"nair","year":"2001"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"303","DOI":"10.1145\/360128.360160","article-title":"Increasing the size of atomic instruction blocks using control flow assertions","author":"patel","year":"2000","journal-title":"Proc 33rd Annu ACM\/IEEE Int Symp Microarchitecture"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694786"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/93542.93550"},{"key":"ref23","article-title":"Dynamic flow instruction cache memory organized around trace segments independent of virtual address line","author":"peleg","year":"1995"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305178"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379260"}],"event":{"name":"35th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-35)","location":"Istanbul, Turkey","acronym":"MICRO-02"},"container-title":["35th Annual IEEE\/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8385\/26403\/01176264.pdf?arnumber=1176264","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,10]],"date-time":"2024-01-10T00:02:18Z","timestamp":1704844938000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1176264\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":39,"URL":"https:\/\/doi.org\/10.1109\/micro.2002.1176264","relation":{},"subject":[]}}