{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T12:56:33Z","timestamp":1742388993371},"reference-count":21,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/micro.2002.1176265","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T11:35:00Z","timestamp":1056627300000},"page":"383-394","source":"Crossref","is-referenced-by-count":22,"title":["Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors"],"prefix":"10.1109","author":[{"given":"A.","family":"Seznec","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Toullec","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"O.","family":"Rochecouste","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"The microarchitecture of the pentium4 processor In Intel Technology Journal","year":"2001","author":"hinton","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"ref12","doi-asserted-by":"crossref","DOI":"10.1145\/279361.279377","article-title":"Pipeline gating: Speculation control for energy reduction","author":"manne","year":"1998","journal-title":"Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA'98)"},{"article-title":"Dynamic register renaming through virtual-physical registers. Journal of Instruction-Level Parallelism","year":"2000","author":"monreal","key":"ref13"},{"key":"ref14","first-page":"206","article-title":"Complexity-effective superscalar processors","author":"subbarao","year":"1997","journal-title":"24th Annual International Symposium on Computer Architecture"},{"journal-title":"A path to complexity-effective wide-issue superscalar processors In Technical Report IRISA PI 1411","year":"2001","author":"seznec","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003587"},{"key":"ref17","article-title":"De-aliased hybrid branch predictors","author":"seznec","year":"1999","journal-title":"Technical Report RR-3618 Inria"},{"key":"ref18","doi-asserted-by":"crossref","DOI":"10.1145\/360128.360136","article-title":"On pipelining dynamic instruction scheduling logic","author":"stark","year":"2000","journal-title":"Proceedings of the 33rd Annual International Symposium on Microarchitecture"},{"key":"ref19","doi-asserted-by":"crossref","DOI":"10.1109\/HICSS.1995.375394","article-title":"A three dimensional register ile for superscalar processors","author":"tremblay","year":"1995","journal-title":"Proceedings of the 28th Annual Hawaii International Conference on System Sciences"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1145\/339647.339708","article-title":"Multiple-banked register ile architectures","author":"cruz","year":"2000","journal-title":"Proceedings of the 27th International Symposium on Computer Architecture"},{"key":"ref3","article-title":"A VLIW architecture for a trace scheduling compiler","author":"robert","year":"1987","journal-title":"Proceedings of Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASP-LOS II)"},{"key":"ref6","article-title":"(Mark Owen) Homewood. Lx: A technology platform for customizable VLIW embedded processing","author":"paolo","year":"2000","journal-title":"Proceedings of the 27th annual international symposium on Computer architecture"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003560"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937452"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645806"},{"key":"ref2","article-title":"Select-free instruction scheduling logic","author":"brown","year":"2001","journal-title":"Proceedings of the 34th Annual International Symposium on Microarchitecture"},{"key":"ref1","article-title":"Reducing the complexity of the register ile in dynamic superscalar processors","author":"balasubramonian","year":"2001","journal-title":"Proceedings of the 34th Annual International Symposium on Microarchitecture"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.535411"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"ref21","doi-asserted-by":"crossref","DOI":"10.1145\/280756.280943","article-title":"The energy complexity of register iles","author":"zyuban","year":"1998","journal-title":"Proceedings of International Symposium on Low Power Electronics and Design (ISLPED"}],"event":{"name":"35th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO-35)","acronym":"MICRO-02","location":"Istanbul, Turkey"},"container-title":["35th Annual IEEE\/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8385\/26403\/01176265.pdf?arnumber=1176265","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,8]],"date-time":"2021-06-08T04:50:13Z","timestamp":1623127813000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1176265\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/micro.2002.1176265","relation":{},"subject":[]}}