{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,26]],"date-time":"2026-08-26T03:29:01Z","timestamp":1787714941038,"version":"build-2784847793"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1109\/micro.2003.1253179","type":"proceedings-article","created":{"date-parts":[[2004,5,25]],"date-time":"2004-05-25T16:11:16Z","timestamp":1085501476000},"page":"7-18","source":"Crossref","is-referenced-by-count":796,"title":["Razor: a low-power pipeline based on circuit-level timing speculation"],"prefix":"10.1109","author":[{"given":"D.","family":"Ernst","sequence":"first","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Nam Sung Kim","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"S.","family":"Das","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"S.","family":"Pant","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"R.","family":"Rao","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Toan Pham","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"C.","family":"Ziesler","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"D.","family":"Blaauw","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"T.","family":"Austin","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"K.","family":"Flautner","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"T.","family":"Mudge","sequence":"additional","affiliation":[{"name":"University of Michigan","place":["Ann Arbor, MI, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Intel SpeedStep Technology","year":"0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1993.393383"},{"key":"ref12","doi-asserted-by":"crossref","DOI":"10.1145\/360128.360166","article-title":"Performance Improvement with Circuit-Level Speculation","author":"liu","year":"2000","journal-title":"Proc 33rd Ann Int'l Symp Microarchitecture (MICRO-33)"},{"key":"ref13","article-title":"Non-Stalling Counterflow Microarchitecture","author":"miller","year":"1998","journal-title":"4th Int Symp High Performance Computer Architecture (HPCA-4)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/2.917539"},{"key":"ref15","article-title":"Modern Control Engineering","author":"ogata","year":"2002"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"76","DOI":"10.1145\/280756.280790","article-title":"The simulation and evaluation of dynamic voltage scaling algorithms","author":"pering","year":"1998","journal-title":"Proceedings 1998 International Symposium on Low Power Electronics and Design (IEEE Cat No 98TH8379) LPE"},{"key":"ref17","article-title":"Digital Integrated Circuits","author":"rabaey","year":"1996","journal-title":"Prentice Hall"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1994.303847"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139166980"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839787"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.604077"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566437"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/5.362752"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1996.507753"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313834"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"ref20","article-title":"LongRun Power Management","year":"0"},{"key":"ref22","article-title":"Achieving Typical Delays in Synchronous Systems via Timing Error Toleration","author":"uht","year":"2000","journal-title":"University of Rhode Island TR-032000–0100"},{"key":"ref21","article-title":"Uniprocessor Performance Enhancement Through Adaptive Clock Frequency Control","author":"uht","year":"2003","journal-title":"2003 International Conference on Advances in Infrastructure for e-Business e-Education e-Science e-Medicine and Mobile Technologies on the Internet (SSGRR 2003w)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052209"},{"key":"ref23","article-title":"Asynchronous Sequential Switching Circuits","author":"unger","year":"1969"},{"key":"ref25","article-title":"Virtex-II Platform FPGA","year":"0"}],"event":{"name":"36th International Symposium on Microarchitecture","location":"San Diego, CA, USA","start":{"date-parts":[[2003,12,5]]},"end":{"date-parts":[[2003,12,5]]}},"container-title":["Proceedings. 36th Annual IEEE\/ACM International Symposium on Microarchitecture, 2003. MICRO-36."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8876\/28039\/01253179.pdf?arnumber=1253179","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,7,27]],"date-time":"2026-07-27T19:15:26Z","timestamp":1785179726000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1253179\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/micro.2003.1253179","relation":{},"subject":[],"published":{"date-parts":[[2003]]}}}