{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:54:37Z","timestamp":1773194077559,"version":"3.50.1"},"reference-count":33,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/micro.2003.1253189","type":"proceedings-article","created":{"date-parts":[[2004,5,25]],"date-time":"2004-05-25T20:11:16Z","timestamp":1085515876000},"page":"129-140","source":"Crossref","is-referenced-by-count":111,"title":["Processor acceleration through automated instruction set customization"],"prefix":"10.1109","author":[{"given":"N.","family":"Clark","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hongtao Zhong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Mahlke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379256"},{"key":"ref32","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1117\/12.221328","article-title":"DISC: The dynamic instruction set computer","author":"wirthlin","year":"1995","journal-title":"Proceedings of Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing"},{"key":"ref31","year":"0","journal-title":"An infrastructure for research in ILP"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167600"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"603","DOI":"10.1109\/12.773797","article-title":"Synthesis of application specific instructions for embedded DSP software","volume":"48","author":"choi","year":"1999","journal-title":"IEEE Transactions on Communications"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICIAP.1999.797762"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/40.848473"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/951710.951730"},{"key":"ref14","article-title":"Instruction set selection for ASIP design","author":"gschwind","year":"1999","journal-title":"ACM CODES Workshop"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624600"},{"key":"ref17","author":"holmer","year":"1993","journal-title":"Automatic Design of Computer Instruction Sets"},{"key":"ref18","article-title":"Synthesis of application specific instruction sets","volume":"14","author":"huang","year":"1995","journal-title":"IEEE TCAD"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/605440.605446"},{"key":"ref28","first-page":"172","article-title":"A high-performance microarchitecture with hardware-programmable function units","author":"razdan","year":"1994","journal-title":"Micro"},{"key":"ref4","doi-asserted-by":"crossref","DOI":"10.1145\/775832.775897","article-title":"Automatic application-specific instruction-set extensions under microarchitectural constraints","author":"atasu","year":"2003","journal-title":"40th DAC"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/43.238612"},{"key":"ref3","author":"arnold","year":"2001","journal-title":"Instruction Set Extensions for Embedded Processors"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CODES.2002.1003617"},{"key":"ref29","author":"seal","year":"2000","journal-title":"ARM Architecture Reference Manual"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/2.204677"},{"key":"ref8","first-page":"5","article-title":"Design of instruction set architctures for support of high-level languages","author":"bose","year":"1984","journal-title":"ISCA"},{"key":"ref7","author":"bennett","year":"1988","journal-title":"A Methodology for Automated Design of Computer Instruction Sets"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/EURDAC.1993.410608"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/581669.581672"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/69558.75700"},{"key":"ref20","article-title":"MediaBench: A tool for evaluating and synthesizing multimedia and communications systems","author":"lee","year":"1997","journal-title":"Micro"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.480146"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/EURDAC.1996.558205"},{"key":"ref24","first-page":"61","article-title":"Adaptive explicitly parallel instruction computing","author":"palem","year":"1999","journal-title":"Proc Australasian Computer Architecture Conference"},{"key":"ref23","first-page":"39","article-title":"Netbench: A benchmarking suite for network processors","author":"memik","year":"2001","journal-title":"ICCAD"},{"key":"ref26","author":"praet","year":"1994","journal-title":"Instruction set definition and instruction selection for ASIP"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2003.1212834"}],"event":{"name":"36th International Symposium on Microarchitecture","location":"San Diego, CA, USA","acronym":"MICRO-03"},"container-title":["22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8876\/28039\/01253189.pdf?arnumber=1253189","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,13]],"date-time":"2024-01-13T13:44:48Z","timestamp":1705153488000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1253189\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/micro.2003.1253189","relation":{},"subject":[]}}