{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,27]],"date-time":"2026-07-27T20:02:40Z","timestamp":1785182560723,"version":"3.55.0"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1109\/micro.2003.1253202","type":"proceedings-article","created":{"date-parts":[[2004,5,25]],"date-time":"2004-05-25T16:11:16Z","timestamp":1085501476000},"page":"277-288","source":"Crossref","is-referenced-by-count":25,"title":["Macro-op scheduling: relaxing scheduling loop constraints"],"prefix":"10.1109","author":[{"given":"I.","family":"Kim","sequence":"first","affiliation":[{"name":"University of Wisconsin","place":["Madison, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M.","family":"Lipasti","sequence":"additional","affiliation":[{"name":"University of Wisconsin","place":["Madison, USA"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003562"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903249"},{"key":"ref12","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2001.991121","article-title":"A high-speed dynamic instruction scheduling scheme for superscalar processors","author":"goshima","year":"2001","journal-title":"Proc 34th Int l Symp Microarchitecture"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"ref14","article-title":"Adapting the SPEC2000 benchmarks suite for simulation-based computer architecture research","author":"kleinosowski","year":"2000","journal-title":"Workshop on Workload Characterization in International Conference on Computer Design"},{"key":"ref15","article-title":"Compaq Computer Corporation","year":"1999","journal-title":"Alpha 21264 Microprocessor Hardware Reference Manual"},{"key":"ref16","doi-asserted-by":"crossref","DOI":"10.1145\/545214.545224","article-title":"An instruction set and microarchitecture for instruction level distributed processing","author":"kim","year":"2002","journal-title":"Proc of International Symposium on Computer Architecture"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/327070.327121"},{"key":"ref18","article-title":"The Intel Pentium M processor: Microarchitecture and performance","volume":"7","author":"gochman","year":"2003","journal-title":"Intel Technology Journal"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335263"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003560"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003558"},{"key":"ref6","article-title":"K7 challenges Intel","volume":"12","author":"diefendorff","year":"1998","journal-title":"Microprocessor Report"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/859622.859623"},{"key":"ref8","article-title":"Select-free instruction scheduling logic","author":"brown","year":"2001","journal-title":"Proc of the International Symposium on Mi-croarchitecture"},{"key":"ref7","article-title":"On pipelining dynamic instruction scheduling logic","author":"stark","year":"2000","journal-title":"Proc 33th Int Symp Microarchitecture"},{"key":"ref2","article-title":"The microarchitecture of the Pentium 4 processor","author":"hinton","year":"2001","journal-title":"Intel Technology Journal Q1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604689"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995719"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003589"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"270","DOI":"10.1109\/ISCA.2000.854397","article-title":"Instruction path coprocessors","author":"yuan chou","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744347"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697011"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742779"},{"key":"ref25","article-title":"The performance potential of data dependence speculation and collapsing","author":"sazeides","year":"1996","journal-title":"Proc of 29th International Symposium on Microarchitecture"}],"event":{"name":"36th International Symposium on Microarchitecture","location":"San Diego, CA, USA","start":{"date-parts":[[2003,12,5]]},"end":{"date-parts":[[2003,12,5]]}},"container-title":["Proceedings. 36th Annual IEEE\/ACM International Symposium on Microarchitecture, 2003. MICRO-36."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8876\/28039\/01253202.pdf?arnumber=1253202","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,7,27]],"date-time":"2026-07-27T19:11:40Z","timestamp":1785179500000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1253202\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/micro.2003.1253202","relation":{},"subject":[],"published":{"date-parts":[[2003]]}}}