{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T13:05:12Z","timestamp":1742389512199},"reference-count":24,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/micro.2003.1253211","type":"proceedings-article","created":{"date-parts":[[2004,5,6]],"date-time":"2004-05-06T16:18:03Z","timestamp":1083860283000},"page":"372-384","source":"Crossref","is-referenced-by-count":20,"title":["Design and implementation of high-performance memory systems for future packet buffers"],"prefix":"10.1109","author":[{"given":"J.","family":"Garcia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Corbal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Cerda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Valero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859653"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339689"},{"journal-title":"Hitachi","article-title":"Hitachi 166 Mhz SDRAM. Hitachi HM5257XXb series","year":"2000","key":"ref12"},{"key":"ref13","article-title":"Designing Buffers for Router Line Cards","author":"iyer","year":"2002","journal-title":"Technical Report TR02-HPNG-031001"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/774763.774782"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.2001.937019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604689"},{"key":"ref18","first-page":"242","article-title":"The Cydra 5 stride-insensitive Memory System","author":"rau","year":"1989","journal-title":"International Conference on Parallel Processing"},{"key":"ref19","article-title":"Cacti 3.0: An integrated cache timing, power and area model","author":"shivakumar","year":"2001","journal-title":"Compaq Computer Corporation Tech Rep"},{"key":"ref4","article-title":"Command-Vector Memory System","author":"corbal","year":"1998","journal-title":"Parallel Architectures and Compilation Techniques PACT"},{"journal-title":"Inside Cisco IOS Software Architecture","year":"2000","author":"bollapragada","key":"ref3"},{"key":"ref6","article-title":"Router\/Switch Architecture with Networking Specific Memories","author":"eatherton","year":"2002","journal-title":"MemCon 2002"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/40.641593"},{"key":"ref8","article-title":"A Conflict-Free Memory Banking Architecture for Fast Packet Buffers","author":"garc\u00eda","year":"2002","journal-title":"Technical Report UPC-DAC-2002-50 UPC"},{"journal-title":"Fujitsu","article-title":"256M bit Double Data Rate FCRAM, MB81N26847B\/261647B-50\/-55\/-60 data sheet","year":"0","key":"ref7"},{"journal-title":"Power NP4GX network processor","year":"0","key":"ref2"},{"journal-title":"Intel IXP2400 Network Processor","year":"0","key":"ref1"},{"key":"ref9","article-title":"Design and Implementation of a 1.2 Gbit\/s ATM Cell Buffer using a Synchronous DRAM chip","author":"glykopoulos","year":"1998","journal-title":"Technical Report 221 ICS-FORTH"},{"key":"ref20","first-page":"343","article-title":"High-Performance Multi-Queue Buffers for VLSI Communication Switches","author":"tamir","year":"0"},{"journal-title":"Network Processor Design Issues and Practices","year":"2002","author":"tsai","key":"ref22"},{"journal-title":"RLDRAM","article-title":"High density, high-bandwidth memory for networking applicacions","year":"0","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/12.381949"},{"key":"ref23","article-title":"Increasing the Number of Strides for Conflict-Free Vector Access","author":"valero","year":"1992","journal-title":"ISCA-19"}],"event":{"name":"36th International Symposium on Microarchitecture","acronym":"MICRO-03","location":"San Diego, CA, USA"},"container-title":["22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8876\/28039\/01253211.pdf?arnumber=1253211","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T21:40:16Z","timestamp":1489441216000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1253211\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/micro.2003.1253211","relation":{},"subject":[]}}