{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,5]],"date-time":"2026-05-05T06:20:08Z","timestamp":1777962008466,"version":"3.51.4"},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/micro.2008.4771796","type":"proceedings-article","created":{"date-parts":[[2009,2,9]],"date-time":"2009-02-09T20:39:10Z","timestamp":1234211950000},"page":"258-269","source":"Crossref","is-referenced-by-count":76,"title":["Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer"],"prefix":"10.1109","author":[{"given":"Livio","family":"Soares","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Tam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Stumm","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2006.302740"},{"key":"17","doi-asserted-by":"crossref","first-page":"222","DOI":"10.1109\/MICRO.1992.697023","article-title":"the effect of page allocation on caches","author":"lynch","year":"1992","journal-title":"Proc 35th Int Symp Microarchitecture (MICRO)"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/216636.216677"},{"key":"15","first-page":"367","article-title":"gaining insights into multi-core cache partitioning: bridging the gap between simulation and real systems","author":"lin","year":"2008","journal-title":"14th Intl Symp on High-Performance Comp Arch (HPCA)"},{"key":"16","author":"lin","year":"2002","journal-title":"Predicting last-touch references under optimal replacement"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70816"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/RTTAS.1997.601360"},{"key":"11","year":"0"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/138873.138876"},{"key":"21","author":"prabhat jain","year":"2001","journal-title":"Controlling cache pollution in prefetching with software-assisted cache replacement"},{"key":"20","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1007\/978-3-540-74309-5_11","article-title":"exploiting single-usage for effective memory management","author":"piquet","year":"2007","journal-title":"Asia-Pacific Computer Systems Architecture Conference"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250709"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305189"},{"key":"24","doi-asserted-by":"crossref","first-page":"186","DOI":"10.1145\/633625.52422","article-title":"multiprocessor cache analysis using atum","author":"sites","year":"1988","journal-title":"International Symposium on Computer Architecture (ISCA)"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1023\/B:SUPE.0000014800.27383.8f"},{"key":"26","article-title":"managing shared l2 caches on multicore systems in software","author":"tarn","year":"2007","journal-title":"Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA)"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476816"},{"key":"28","doi-asserted-by":"crossref","first-page":"154","DOI":"10.1109\/REAL.2003.1253263","article-title":"data caches in multitasking hard real-time systems","author":"vera","year":"2003","journal-title":"24th IEEE International Real-Time Systems Symposium (RTSS)"},{"key":"29","first-page":"315","article-title":"software-based cache partitioning for real-time applications","volume":"2","author":"wolfe","year":"1994","journal-title":"Journal of Computer and Software Engineering"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1064212.1064232"},{"key":"2","author":"bailey","year":"1995","journal-title":"The NAS Parallel Benchmarks 2 0"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/224538.224622"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/265924.265925"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2000.824338"},{"key":"7","first-page":"455","article-title":"managing distributed, shared l2 caches through os-level page allocation","author":"cho","year":"2006","journal-title":"39th Intl Symp on Microarchitecture (MICRO)"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/HICSS.1989.47168"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.14"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.27"},{"key":"31","first-page":"134","article-title":"compiler managed micro-cache bypassing for high performance epic processors","author":"wu","year":"2002","journal-title":"Proc Int Symp Microarch (MICRO)"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237195"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1007\/11859802_6"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645821"}],"event":{"name":"2008 41st IEEE\/ACM International Symposium on Microarchitecture (MICRO)","location":"Como, Italy","start":{"date-parts":[[2008,11,8]]},"end":{"date-parts":[[2008,11,12]]}},"container-title":["2008 41st IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4757685\/4771764\/04771796.pdf?arnumber=4771796","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,17]],"date-time":"2019-05-17T22:51:18Z","timestamp":1558133478000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4771796\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/micro.2008.4771796","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}