{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:38:52Z","timestamp":1772725132824,"version":"3.50.1"},"reference-count":42,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/micro.2008.4771800","type":"proceedings-article","created":{"date-parts":[[2009,2,9]],"date-time":"2009-02-09T20:39:10Z","timestamp":1234211950000},"page":"306-317","source":"Crossref","is-referenced-by-count":33,"title":["A performance-correctness explicitly-decoupled architecture"],"prefix":"10.1109","author":[{"given":"Alok","family":"Garg","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael C.","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","first-page":"213","article-title":"paceline: improving single-thread performance in nanoscale cmps through core overclocking","author":"greskamp","year":"2007","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"key":"35","doi-asserted-by":"crossref","first-page":"469","DOI":"10.1145\/1080695.1070009","article-title":"store buffer design in first-level multibanked data caches","author":"torres","year":"2005","journal-title":"Proc Int Symp Comput Archit"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1147\/rd.461.0005"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.46"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.23"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360153"},{"key":"15","year":"0"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003562"},{"key":"16","year":"0"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263597"},{"key":"13","year":"0"},{"key":"14","first-page":"198","article-title":"understanding scheduling replay schemes","author":"kim","year":"2004","journal-title":"Proc Int Symp High-Perform Comput Arch"},{"key":"37","first-page":"423","article-title":"checkpoint processing and recovery: towards scalable large instruction window processors","author":"akkary","year":"2003","journal-title":"Proc Int'l Symp on Microarch"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.11"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253244"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183532"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253243"},{"key":"20","first-page":"269","article-title":"a study of slipstream processors","author":"purser","year":"2000","journal-title":"Proc Int'l Symp on Microarch"},{"key":"42","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.31"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.9"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2004.3"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/1111583.1111591"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1274005"},{"key":"24","article-title":"assisted execution","author":"dubois","year":"1998"},{"key":"25","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1145\/384285.379251","article-title":"data prefetching by dependence graph precomputation","author":"annavaram","year":"2001","journal-title":"Proc Int Symp Comput Archit"},{"key":"26","doi-asserted-by":"crossref","first-page":"40","DOI":"10.1145\/384285.379250","article-title":"tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors","author":"luk","year":"2001","journal-title":"Proc Int Symp Comput Archit"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937426"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765950"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937427"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1002\/1097-024X(200101)31:1<67::AID-SPE357>3.0.CO;2-A"},{"key":"1","doi-asserted-by":"crossref","DOI":"10.1109\/MICRO.2005.37","article-title":"complexity: estimating processor design effort","author":"bazeghi","year":"2005","journal-title":"Proc Int Symp Microarchitecture"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903250"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/357401.357403"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742769"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176241"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1145\/377792.377856"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859640"},{"key":"9","first-page":"231","article-title":"dual-core execution: building a highly scalable single-thread instruction window","author":"zhou","year":"2005","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"key":"8","year":"0"}],"event":{"name":"2008 41st IEEE\/ACM International Symposium on Microarchitecture (MICRO)","location":"Como, Italy","start":{"date-parts":[[2008,11,8]]},"end":{"date-parts":[[2008,11,12]]}},"container-title":["2008 41st IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4757685\/4771764\/04771800.pdf?arnumber=4771800","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,17]],"date-time":"2019-05-17T22:51:10Z","timestamp":1558133470000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4771800\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":42,"URL":"https:\/\/doi.org\/10.1109\/micro.2008.4771800","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}