{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:18:40Z","timestamp":1771697920408,"version":"3.50.1"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/micro.2008.4771801","type":"proceedings-article","created":{"date-parts":[[2009,2,9]],"date-time":"2009-02-09T15:39:10Z","timestamp":1234193950000},"page":"318-329","source":"Crossref","is-referenced-by-count":181,"title":["Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach"],"prefix":"10.1109","author":[{"given":"Ramazan","family":"Bitirgen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Engin","family":"Ipek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jose F.","family":"Martinez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"15","article-title":"balancing throughput and fairness in smt processors","author":"luo","year":"2001","journal-title":"Proceedings of the International Symposium on Performance Analysis of Systems and Software"},{"key":"16","year":"2006","journal-title":"512Mb DDR2 SDRAM Component Data Sheet MT47H128M4B6-25"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598114"},{"key":"14","article-title":"organizing the last line of defense before hitting the memory wall for cmps","author":"liu","year":"2004","journal-title":"HPCA-10"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1006209.1006246"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2004.1342546"},{"key":"21","article-title":"utility-based cache partitioning: a low-overhead, high-performance, runtime mechanism to partition shared caches","author":"qureshi","year":"2006","journal-title":"MICRO-39"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250671"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152160"},{"key":"23","author":"renau","year":"0","journal-title":"SESC Simulator"},{"key":"24","first-page":"128","article-title":"Memory access scheduling","author":"rixner","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995703"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1504\/IJES.2009.027939"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086328"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1016\/B978-1-55860-335-6.50012-X"},{"key":"2","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.8"},{"key":"1","article-title":"nas parallel benchmarks. technical report, nasa ames research center","author":"bailey","year":"1994"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/2.869367"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696229"},{"key":"5","article-title":"learning-based smt processor resource distribution via hill-climbing","author":"choi","year":"2006","journal-title":"ISCA-33"},{"key":"4","article-title":"thermal-effective clustered microarchitectures","author":"chaparro","year":"2004","journal-title":"Workshop on Temperature-Aware Computer Systems"},{"key":"9","first-page":"878","article-title":"Compact thermal modeling for temperature-aware design","author":"wei huang","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601916"}],"event":{"name":"2008 41st IEEE\/ACM International Symposium on Microarchitecture (MICRO)","location":"Como, Italy","start":{"date-parts":[[2008,11,8]]},"end":{"date-parts":[[2008,11,12]]}},"container-title":["2008 41st IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4757685\/4771764\/04771801.pdf?arnumber=4771801","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T14:43:00Z","timestamp":1489761780000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4771801\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/micro.2008.4771801","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}