{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T11:48:04Z","timestamp":1763466484377},"reference-count":52,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/micro.2008.4771807","type":"proceedings-article","created":{"date-parts":[[2009,2,9]],"date-time":"2009-02-09T15:39:10Z","timestamp":1234193950000},"page":"388-398","source":"Crossref","is-referenced-by-count":10,"title":["Evaluating the effects of cache redundancy on profit"],"prefix":"10.1109","author":[{"given":"Abhishek","family":"Das","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Berkin","family":"Ozisikyilmaz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Serkan","family":"Ozdemir","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gokhan","family":"Memik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joseph","family":"Zambreno","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alok","family":"Choudhary","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"35","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231840"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2005.10"},{"key":"33","first-page":"448","article-title":"A methodology to improve timing yield in the presence of process variations","author":"raj","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.89"},{"key":"39","doi-asserted-by":"crossref","first-page":"481","DOI":"10.1109\/ICCD.2003.1240944","article-title":"exploiting microarchitectural redundancy for defect tolerance","author":"shivakumar","year":"2003","journal-title":"International Conference on Computer Design (ICCD)"},{"year":"0","key":"37"},{"key":"38","doi-asserted-by":"crossref","DOI":"10.1145\/1366230.1366257","article-title":"reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching","author":"romanescu","year":"2008","journal-title":"ACM International Conference on Computing Frontiers"},{"journal-title":"OpenSPARC T1","year":"0","author":"sun","key":"43"},{"year":"0","key":"42"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1109\/12.21141"},{"key":"40","article-title":"cacti 3.0: an integrated cache timing, power, and area model","author":"shivakumar","year":"0","journal-title":"WRL Research Report"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601905"},{"key":"23","article-title":"mitigating the impact of process variations on cpu register file and execution units","author":"liang","year":"2006","journal-title":"International Symposium on Microarchitecture"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.27"},{"journal-title":"Manufacturing-aware Design Helps Boost IC Yield","year":"0","author":"miller","key":"26"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803943"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2001.929760"},{"key":"29","first-page":"73","article-title":"process variations and their impact on circuit operation","author":"natarajan","year":"1999","journal-title":"International Symposium on Defect and Fault Tolerance in VLSI Systems"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/4.823443"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809463"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840407"},{"journal-title":"The UltraSPARC T1 Processor-Reliability Availability and Serviceability","year":"0","author":"bryg","key":"7"},{"key":"30","article-title":"yield-aware cache architectures","author":"ozdemir","year":"2006","journal-title":"International Symposium on Microarchitecture"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"32","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/LPE.2000.155259","article-title":"gated-v\/sub dd\/: a circuit technique to reduce leakage in deep-submicron cache memories","author":"powell","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057752"},{"journal-title":"Processor Price Prediction Models","year":"0","author":"ozisikylmaz","key":"31"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996695"},{"key":"8","first-page":"201","article-title":"new paradigm of predictive mosfet and interconnect modeling for early circuit design","author":"cao","year":"2000","journal-title":"Custom Integrated Circuits Conference"},{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2001.937453"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168882"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/325096.325162"},{"key":"15","article-title":"impact of parameter variations on multi-core chips","author":"humenay","year":"2006","journal-title":"Workshop on Architectural Support for Gigascale Integration"},{"year":"0","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003572"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.82"},{"key":"11","article-title":"mitigating the effects of process variations: architectural approaches for improving batch performance","author":"das","year":"2007","journal-title":"presented at Workshop on Architectural Support for Gigascale Integration (ASGI)"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2006.1594770"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168881"},{"key":"20","first-page":"627","article-title":"leakage power optimization techniques for ultra deep sub-micron multi-level caches","author":"kim","year":"2003","journal-title":"International Conference on Computer Aided Design"},{"key":"49","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.152"},{"key":"48","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250703"},{"journal-title":"Introduction to Data Mining","year":"2005","author":"tan","key":"45"},{"key":"44","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1009882"},{"year":"0","key":"47"},{"key":"46","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.40"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1996.494151"},{"key":"51","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903259"},{"key":"52","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1109\/HPCA.2002.995706","article-title":"exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay","author":"yang","year":"2002","journal-title":"International Symposium on High-Performance Computer Architecture"},{"key":"50","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.122"}],"event":{"name":"2008 41st IEEE\/ACM International Symposium on Microarchitecture (MICRO)","start":{"date-parts":[[2008,11,8]]},"location":"Como, Italy","end":{"date-parts":[[2008,11,12]]}},"container-title":["2008 41st IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4757685\/4771764\/04771807.pdf?arnumber=4771807","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T07:56:56Z","timestamp":1633075016000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4771807\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":52,"URL":"https:\/\/doi.org\/10.1109\/micro.2008.4771807","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}