{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T11:48:01Z","timestamp":1763466481568},"reference-count":42,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/micro.2008.4771808","type":"proceedings-article","created":{"date-parts":[[2009,2,9]],"date-time":"2009-02-09T20:39:10Z","timestamp":1234211950000},"page":"399-410","source":"Crossref","is-referenced-by-count":10,"title":["NBTI tolerant microarchitecture design in the presence of process variation"],"prefix":"10.1109","author":[{"family":"Xin Fu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Tao Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jose","family":"Fortes","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","article-title":"latency adaptation for multiported register files to mitigate the impact of process varations","author":"liang","year":"2006","journal-title":"Workshop on ASGI"},{"key":"35","doi-asserted-by":"crossref","first-page":"364","DOI":"10.1145\/1278480.1278573","article-title":"The Impact of NBTI on the Performance of Combinational and Sequential Circuits","author":"wenping wang","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2003.1197712"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1016\/S0967-0661(99)00053-2"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2003.1197714"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"15","article-title":"impact of negative bias temperature instability on digital circuit reliability","author":"reddy","year":"2002","journal-title":"proceedings of IRPS"},{"journal-title":"Impact of NBTI on SRAM Read Stability and Design for Reliability ISQED","year":"2006","author":"kumar","key":"34"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147172"},{"key":"39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.30"},{"key":"13","article-title":"mitigating the impact of process variations on processor register files and execution units","author":"liang","year":"2006","journal-title":"Proceedings of MICRO"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.43"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366179"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/43.998626"},{"key":"38","article-title":"nbti-resilient memory cells with nand gates for highly-ported structures","author":"abella","year":"2007","journal-title":"Workshop on DSN"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065716"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/5.843000"},{"key":"20","doi-asserted-by":"crossref","first-page":"934","DOI":"10.1145\/1278480.1278710","article-title":"variation resilient low-power circuit design methodology using on-chip phase locked loop","author":"kunhyuk kang","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"42","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"journal-title":"Impact of Process Variations and Long Term Degradation on 6T-SRAM Cells Advances in Radio Science","year":"2007","author":"fischer","key":"41"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2007.85"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560162"},{"journal-title":"Characterization of NBTI induced Temporal Performance Degradation in Nano-Scale SRAM array using I DDQ IEEE International Test Conference","year":"2007","author":"kang","key":"23"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.82"},{"key":"25","article-title":"yield-aware cache architectures","author":"ozdemir","year":"2006","journal-title":"Proceedings of MICRO"},{"key":"26","article-title":"path-based statistical timing analysis considering inter and intra-die correlations","author":"agarwal","year":"2002","journal-title":"Proc TAU"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2006.4271847"},{"key":"28","article-title":"the road ahead: variability","author":"kahng","year":"2002","journal-title":"Design and Test of Computers"},{"journal-title":"Arizona State Univeristy","year":"0","key":"29"},{"year":"0","key":"3"},{"journal-title":"A Growing Threat to Device Reliability Semiconductor International","year":"2004","author":"peters","key":"2"},{"journal-title":"Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration Journal of Solid-State Circuits","year":"2002","author":"bowman","key":"10"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1567461"},{"key":"30","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"7","article-title":"an efficient method to identify critical gates under circuit aging","author":"wang","year":"2007","journal-title":"Proceedings of ICCAD"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.21"},{"year":"0","key":"32"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.104"},{"article-title":"hotleakage: a temperature-aware model of subthreshold and gate leakage for architects","year":"2003","author":"zhang","key":"31"},{"key":"4","article-title":"an analytical model for negative bias temperature instability","author":"kumar","year":"2006","journal-title":"Proceedings of ICCAD"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.11"}],"event":{"name":"2008 41st IEEE\/ACM International Symposium on Microarchitecture (MICRO)","start":{"date-parts":[[2008,11,8]]},"location":"Como, Italy","end":{"date-parts":[[2008,11,12]]}},"container-title":["2008 41st IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4757685\/4771764\/04771808.pdf?arnumber=4771808","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T16:36:18Z","timestamp":1497803778000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4771808\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":42,"URL":"https:\/\/doi.org\/10.1109\/micro.2008.4771808","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}