{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T06:10:12Z","timestamp":1744179012059,"version":"3.28.0"},"reference-count":37,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/micro.2016.7783707","type":"proceedings-article","created":{"date-parts":[[2016,12,19]],"date-time":"2016-12-19T17:11:05Z","timestamp":1482167465000},"page":"1-12","source":"Crossref","is-referenced-by-count":5,"title":["Register sharing for equality prediction"],"prefix":"10.1109","author":[{"given":"Arthur","family":"Perais","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fernando A.","family":"Endo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andre","family":"Seznec","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/280756.280943"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598118"},{"key":"ref31","article-title":"A case for (partially) TAgged GEometric history length branch prediction","volume":"8","author":"seznec","year":"2006","journal-title":"Journal of Instruction Level Parallelism"},{"journal-title":"Standard Performance Evaluation Corporation","year":"2006","key":"ref30"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694770"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250704"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003587"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.39"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446105"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169033"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.15"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1999.807407"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765940"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694787"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/290409.290411"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903264"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1998.727186"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.43"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566464"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176237"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237173"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056018"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.19"},{"key":"ref5","article-title":"Speculative execution based on value prediction","author":"mendelson","year":"1997","journal-title":"Technion-Israel Institute of Technology"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665742"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835952"},{"journal-title":"Intel (2014 September) Software optimization manual","year":"0","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765957"},{"journal-title":"Intel 64 and IA-32 architectures software developer's manual","year":"2013","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645815"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742782"},{"key":"ref21","article-title":"Implementations of context based value predictors","author":"sazeides","year":"1998","journal-title":"Department of Electrical and Computer Engineering University of Wisconsin-Madison"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859656"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645819"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742783"},{"key":"ref25","article-title":"A 64-Kbytes ITTAGE indirect branch predictor","author":"seznec","year":"2011","journal-title":"Journal of Instruction-Level Parallelism"}],"event":{"name":"2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","start":{"date-parts":[[2016,10,15]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2016,10,19]]}},"container-title":["2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7777315\/7783693\/07783707.pdf?arnumber=7783707","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,16]],"date-time":"2019-09-16T14:51:37Z","timestamp":1568645497000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7783707\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/micro.2016.7783707","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}