{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:46:37Z","timestamp":1772725597008,"version":"3.50.1"},"reference-count":44,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/micro.2016.7783730","type":"proceedings-article","created":{"date-parts":[[2016,12,19]],"date-time":"2016-12-19T17:11:05Z","timestamp":1482167465000},"page":"1-12","source":"Crossref","is-referenced-by-count":15,"title":["Improving energy efficiency of DRAM by exploiting half page row access"],"prefix":"10.1109","author":[{"given":"Heonjae","family":"Ha","sequence":"first","affiliation":[]},{"given":"Ardavan","family":"Pedram","sequence":"additional","affiliation":[]},{"given":"Stephen","family":"Richardson","sequence":"additional","affiliation":[]},{"given":"Shahar","family":"Kvatinsky","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Horowitz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"1","article-title":"Exploiting refresh effect of DRAM read operations: A practical approach to low-power refresh","author":"gong","year":"2015","journal-title":"Computers IEEE Transactions"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237001"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2629677"},{"key":"ref32","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","article-title":"SPEC CPU2006 benchmark descriptions","volume":"34","author":"henning","year":"2006","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref31","article-title":"DDR4_Power_Calc. XLSM","year":"2014"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.164"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598122"},{"key":"ref35","article-title":"8Gb B-die DDR4 SDRAM datasheet rev. 1.11","year":"2015"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"ref10","first-page":"42","article-title":"A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture","author":"lim","year":"0"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750408"},{"key":"ref11","first-page":"128","article-title":"1.2V 1.6Gb\/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I\/O sense amplifier and segmented sub-array architecture","author":"moon","year":"0"},{"key":"ref12","article-title":"4Gb DDR4 SDRAM datasheet","year":"0"},{"key":"ref13","year":"2012"},{"key":"ref14","author":"moon","year":"2013"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853217"},{"key":"ref16","article-title":"TN-47-10: DDR2 posted CAS# additive latency introduction","year":"0"},{"key":"ref17","article-title":"Semiconductor memory device with sense amplifier driver having multiplied output lines","author":"kang","year":"2006"},{"key":"ref18","article-title":"Impact of processing technology on dram sense amplifier design","author":"gealow","year":"1990"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/4.293118"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDER.2005.1546614"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2133382.2133386"},{"key":"ref27","article-title":"4Gb D-die DDR4 SDRAM datasheet rev. 1.7","year":"2015"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2008.13"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176869"},{"key":"ref29","article-title":"USIMM: The Utah simulated memory module","author":"chatterjee","year":"2012","journal-title":"University of Utah Tech Rep"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1179900"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815983"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522354"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155624"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/9780470544426"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237004"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337202"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.42"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1992.307481"},{"key":"ref24","article-title":"DDR3L-RS: Reducing DRAM power consumption in standby","year":"0"},{"key":"ref41","doi-asserted-by":"crossref","first-page":"336","DOI":"10.1109\/IEDM.1987.191425","article-title":"a meta-stable leakage phenomenon in dram charge storage &#8212;variable hold time","author":"yaney","year":"1987","journal-title":"1987 International Electron Devices Meeting"},{"key":"ref23","article-title":"Under the hood: DRAM architectures: 8F2 vs. 6F2","author":"choi","year":"0"},{"key":"ref44","doi-asserted-by":"crossref","first-page":"361","DOI":"10.1145\/2678373.2665726","article-title":"Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors","author":"kim","year":"2014","journal-title":"Proceeding of the 41st annual international symposium on Computer architecuture"},{"key":"ref26","article-title":"Inside Intel next generation Nehalem microarchitecture","volume":"20","author":"singhal","year":"2008","journal-title":"Hot Chips"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"ref25","year":"2015"}],"event":{"name":"2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","location":"Taipei, Taiwan","start":{"date-parts":[[2016,10,15]]},"end":{"date-parts":[[2016,10,19]]}},"container-title":["2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7777315\/7783693\/07783730.pdf?arnumber=7783730","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,16]],"date-time":"2019-09-16T14:51:51Z","timestamp":1568645511000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7783730\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":44,"URL":"https:\/\/doi.org\/10.1109\/micro.2016.7783730","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}