{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T23:06:03Z","timestamp":1747868763365},"reference-count":40,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/micro.2016.7783744","type":"proceedings-article","created":{"date-parts":[[2016,12,19]],"date-time":"2016-12-19T17:11:05Z","timestamp":1482167465000},"page":"1-13","source":"Crossref","is-referenced-by-count":21,"title":["Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation"],"prefix":"10.1109","author":[{"given":"Animesh","family":"Jain","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Parker","family":"Hill","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shih-Chieh","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Muneeb","family":"Khan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Md E.","family":"Haque","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael A.","family":"Laurenzano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Scott","family":"Mahlke","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lingjia","family":"Tang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason","family":"Mars","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","article-title":"Expressing and verifying probabilistic assertions","author":"sampson","year":"2014","journal-title":"Programming Language Design and Implementation (PLDI)"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1772954.1772987"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598122"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2015.7324549"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950391"},{"key":"ref30","article-title":"Load value approximation","author":"san","year":"2014","journal-title":"International Symposium on Microarchitecture (MICRO)"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503296"},{"key":"ref36","article-title":"Learning both weights and connections for efficient neural networks","author":"han","year":"2015","journal-title":"ArXiv 1506 02626"},{"key":"ref35","article-title":"Deep learning with limited numerical precision","author":"gupta","year":"2015","journal-title":"arXiv 1502 02551"},{"key":"ref34","article-title":"Low precision arithmetic for deep learning","author":"courbariaux","year":"0","journal-title":"arXiv 1412 7024 2014"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"377","DOI":"10.1145\/2370816.2370870","article-title":"Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches","author":"gennady pekhimenko","year":"2012","journal-title":"In International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540715"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541958"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.41"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830790"},{"article-title":"Computer organization and design: the hardware\/software interface","year":"2013","author":"patterson","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993518"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.48"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830810"},{"key":"ref18","doi-asserted-by":"crossref","DOI":"10.7873\/DATE.2015.0513","article-title":"Axilog: Language support for approximate hardware design","author":"yazdanbakhsh","year":"2015","journal-title":"Design Automation and Test in Europe (DATE)"},{"key":"ref19","article-title":"Verifying quantitative reliability for programs that execute on unreliable hardware","author":"carbin","year":"2013","journal-title":"Object Oriented Programming Systems Languages and Applications (OOPSLA)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540712"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694347"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151008"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1806596.1806620"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2908080.2908087"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950390"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488873"},{"key":"ref9","doi-asserted-by":"crossref","DOI":"10.1145\/2678373.2665696","article-title":"Sc2: A statistical compression cache scheme","author":"arelakis","year":"2014","journal-title":"International Symposium on Computer Architecuture (MI-CRO)"},{"key":"ref1","article-title":"Best-effort parallel execution framework for recognition and mining applications","author":"meng","year":"2009","journal-title":"Proc Int l Parallel and Distributed Processing Symp (IPDPS)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/InPar.2012.6339595"},{"key":"ref22","doi-asserted-by":"crossref","DOI":"10.1145\/2024716.2024718","article-title":"The Gem5 simulator","author":"binkert","year":"2011","journal-title":"SIGARCH ComputerArchitecture News"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref24","article-title":"Cacti 6.0: A tool to model large caches","author":"muralimanohar","year":"2009","journal-title":"HP Laboratories"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref26","article-title":"International technology roadmap for semiconductors (ITRS) symposium","author":"ravindra","year":"2001","journal-title":"Journal of Electronic Materials"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/277650.277661"}],"event":{"name":"2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","start":{"date-parts":[[2016,10,15]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2016,10,19]]}},"container-title":["2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7777315\/7783693\/07783744.pdf?arnumber=7783744","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T20:32:39Z","timestamp":1658176359000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7783744\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/micro.2016.7783744","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}