{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,4]],"date-time":"2026-07-04T22:28:39Z","timestamp":1783204119116,"version":"3.54.6"},"reference-count":65,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/micro.2016.7783753","type":"proceedings-article","created":{"date-parts":[[2016,12,19]],"date-time":"2016-12-19T17:11:05Z","timestamp":1482167465000},"page":"1-13","source":"Crossref","is-referenced-by-count":105,"title":["Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems"],"prefix":"10.1109","author":[{"given":"Hadi","family":"Asghari-Moghaddam","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Young Hoon","family":"Son","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jung Ho","family":"Ahn","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nam Sung","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2000.854387"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISBI.2008.4541126"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757501"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2014.7040988"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"ref30","article-title":"Memory-centric System Interconnect Design with Hybrid Memory Cubes","author":"kim","year":"2013","journal-title":"International Conference on Parallel Architectures and Compilation Techniques"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref36","article-title":"A Processing in Memory Taxonomy and a Case for Studying Fixed-function PIM","author":"loh","year":"2013","journal-title":"Workshop on Near-Data Processing"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2445572.2445577"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056057"},{"key":"ref60","article-title":"BOOM: Enabling Mobile Memory Based Low-Power Server DIMMs","author":"yoon","year":"2012","journal-title":"ISCA"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000100"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736064"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1999.808425"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2028948"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2013.6702348"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"},{"key":"ref2","article-title":"Samsung DDR4 SDRAM","year":"0"},{"key":"ref1","article-title":"CORAL Benchmark Codes","year":"0"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056040"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485939"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346190"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.10"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155660"},{"key":"ref26","article-title":"Introducing LRDIMM - A New Class of Memory Modules","year":"0","journal-title":"Inphi"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844483"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522329"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062937"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.15"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380850"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306794"},{"key":"ref54","article-title":"Parboil: A Revised Benchmark Suite for Scientific and Commercial Throughput Computing","author":"stratton","year":"2012","journal-title":"Center for Reliable and High-Performance Computing"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2010.69"},{"key":"ref52","first-page":"162","article-title":"Rethinking Design Metrics for Datacenter DRAM","author":"sodani","year":"2015","journal-title":"ACM International Symposium on Memory Systems (MEMSYS)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2013.2283277"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509675"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237004"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691198"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref14","article-title":"High-level Programming Model Abstractions for Processing in Memory","author":"chu","year":"2013","journal-title":"Workshop on Near-Data Processing"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/192161.192194"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.8"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514197"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/eScience.2008.59"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1992.591879"},{"key":"ref4","article-title":"JEDEC Standard: DDR4 SDRAM","year":"2012"},{"key":"ref3","article-title":"JEDEC Standard: DDR2 SDRAM Fully Buffered DIMM (FBDIMM) Design Specification","year":"2007"},{"key":"ref6","article-title":"JEDEC Standard: Low Power Double Data Rate 4 (LPDDR4)","year":"2014"},{"key":"ref5","article-title":"JEDEC Standard: DDR4 SDRAM Load Reduced DIMM (LRDIMM) Design Specification","year":"2014"},{"key":"ref8","article-title":"A 60nm 6Gb\/s\/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI\/SSN-Reduction Techniques","author":"bae","year":"2008","journal-title":"IEEE International Solid-State Circuits Conference (ISSCC)"},{"key":"ref7","article-title":"A Logic-base Interconnect for Supporting Near Memory Computation in the Hybrid Memory Cube","author":"azarkhish","year":"2014","journal-title":"Workshop on Near-Data Processing"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.54"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485943"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1997.628842"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485935"},{"key":"ref48","article-title":"Hybrid Memory Cube","author":"pawlowski","year":"2011","journal-title":"Hot Chips"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"ref42","article-title":"Micron Z80A 4Gb DDR4 × 8 Package DQ S-parameters","year":"2015","journal-title":"Micron"},{"key":"ref41","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-45234-8_7","article-title":"ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix","author":"mei","year":"2003","journal-title":"Field Programmable Logic and Application 13th International Conference"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694774"},{"key":"ref43","article-title":"Design Technologies for a 1.2V 2.4Gb\/s\/pin High Capacity DDR4 SDRAM with TSVs","author":"oh","year":"2014","journal-title":"IEEE Symposium on VLSI Circuits"}],"event":{"name":"2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","location":"Taipei, Taiwan","start":{"date-parts":[[2016,10,15]]},"end":{"date-parts":[[2016,10,19]]}},"container-title":["2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7777315\/7783693\/07783753.pdf?arnumber=7783753","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,16]],"date-time":"2019-09-16T14:51:36Z","timestamp":1568645496000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7783753\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":65,"URL":"https:\/\/doi.org\/10.1109\/micro.2016.7783753","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}