{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T02:48:51Z","timestamp":1729651731463,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/mixdes.2015.7208537","type":"proceedings-article","created":{"date-parts":[[2015,8,20]],"date-time":"2015-08-20T17:45:09Z","timestamp":1440092709000},"page":"330-333","source":"Crossref","is-referenced-by-count":1,"title":["Fast and accurate fractional frequency synthesizer in 0.18&amp;#x03BC;m technology"],"prefix":"10.1109","author":[{"given":"Mehdi","family":"Ghasemzadeh","sequence":"first","affiliation":[]},{"given":"Arefeh","family":"Soltani","sequence":"additional","affiliation":[]},{"given":"Amin","family":"Akbari","sequence":"additional","affiliation":[]},{"given":"Khayrollah","family":"Hadidi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","DOI":"10.1109\/CICC.2002.1012864","article-title":"A 1.8 GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCO","volume":"427","author":"heng","year":"2002","journal-title":"Custom Integrated Circuits Conference 2002 Proceedings of the IEEE 2002"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2014.6872173"},{"journal-title":"Design of Analog CMOS Integrated Circuits McGraw-Hill","year":"2001","author":"razavi","key":"ref12"},{"journal-title":"Monolithic Phase-Locked Loops and Clock Recovery Circuits","year":"2003","author":"razavi","key":"ref13"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SSST.2006.1619042"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.726549"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ACC.2002.1024569"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ACC.2003.1243435"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.509852"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807398"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.753684"},{"key":"ref1","first-page":"168","article-title":"A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application","author":"hwang","year":"2000","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2012.6407004"}],"event":{"name":"2015 MIXDES - 22nd International Conference \"Mixed Design of Integrated Circuits & Systems\"","start":{"date-parts":[[2015,6,25]]},"location":"Torun, Poland","end":{"date-parts":[[2015,6,27]]}},"container-title":["2015 22nd International Conference Mixed Design of Integrated Circuits &amp; Systems (MIXDES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7168332\/7208464\/07208537.pdf?arnumber=7208537","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T14:01:29Z","timestamp":1498226489000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7208537\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/mixdes.2015.7208537","relation":{},"subject":[],"published":{"date-parts":[[2015,6]]}}}