{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:04:28Z","timestamp":1742382268465,"version":"3.38.0"},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2002,5,1]],"date-time":"2002-05-01T00:00:00Z","timestamp":1020211200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Micro"],"published-print":{"date-parts":[[2002,5]]},"DOI":"10.1109\/mm.2002.1013302","type":"journal-article","created":{"date-parts":[[2002,10,18]],"date-time":"2002-10-18T21:39:07Z","timestamp":1034977147000},"page":"32-40","source":"Crossref","is-referenced-by-count":3,"title":["Intelligent-memory architecture for artificial neural networks"],"prefix":"10.1109","volume":"22","author":[{"given":"J.","family":"Buddefeld","sequence":"first","affiliation":[]},{"given":"K.E.","family":"Grosspietsch","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-1619-0"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3994-0"},{"volume-title":"Silicon Architectures for Neural Nets","year":"1991","author":"Sami","key":"ref3"},{"key":"ref4","first-page":"9","article-title":"High Speed Neural Network Chip on PCI-Board","volume-title":"Proc. 6th Int\u2019l Conf. Microelectronics for Neural Networks, Evolutionary and Fuzzy Systems","author":"Eppler","year":"1997"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(92)90070-4"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/54.748803"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"issue":"216","key":"ref9","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-16445-6","volume-title":"LUCAS Associative Array Processor: Design, Programming and Application Studies, Lecture Notes in Computing Science","author":"Fernstrom","year":"1986"},{"key":"ref10","first-page":"159","article-title":"Orthogonal Memory: A Step Toward Realization of Large Capacity Associative Memory","volume-title":"Proc. Int\u2019l Conf. VLSI Design","author":"Kokubu","year":"1985"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/40.141599"},{"key":"ref12","first-page":"211","article-title":"An Architecture for an Intelligent Multi-Mode WSI Memory","volume-title":"Proc. Int\u2019l Conf. Wafer-Scale Integration","author":"Grosspietsch","year":"1990"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/40.180248"},{"issue":"5","key":"ref14","first-page":"264","article-title":"Ortsadressierbarer Assoziativspeicher [Location-Addressable Associative Memory]","volume":"27","author":"Tavangarian","year":"1985","journal-title":"Elektronische Rechenanlagen [Electronic Computers]"}],"container-title":["IEEE Micro"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/40\/21821\/01013302.pdf?arnumber=1013302","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,15]],"date-time":"2025-03-15T05:10:23Z","timestamp":1742015423000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1013302\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,5]]},"references-count":14,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/mm.2002.1013302","relation":{},"ISSN":["0272-1732","1937-4143"],"issn-type":[{"type":"print","value":"0272-1732"},{"type":"electronic","value":"1937-4143"}],"subject":[],"published":{"date-parts":[[2002,5]]}}}