{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:03:57Z","timestamp":1742097837656,"version":"3.38.0"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2002,9,1]],"date-time":"2002-09-01T00:00:00Z","timestamp":1030838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Micro"],"published-print":{"date-parts":[[2002,9]]},"DOI":"10.1109\/mm.2002.1044300","type":"journal-article","created":{"date-parts":[[2003,1,3]],"date-time":"2003-01-03T17:55:00Z","timestamp":1041616500000},"page":"56-68","source":"Crossref","is-referenced-by-count":12,"title":["A polymorphous computing fabric"],"prefix":"10.1109","volume":"22","author":[{"given":"C.","family":"Wolinski","sequence":"first","affiliation":[]},{"given":"M.","family":"Gokhale","sequence":"additional","affiliation":[]},{"given":"K.","family":"McCave","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"volume-title":"Theory of Self-Reproducing Automata","year":"1966","author":"von Neumann","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/92.486081"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707876"},{"key":"ref4","first-page":"126","article-title":"RaPiD-Reconfigurable Pipelined Data Path","volume-title":"Field-Programmable Logic: Smart Applications, New Paradigms, and Compilers: 6th Int\u2019l Workshop Field-Programmable Logic and Applications","author":"Green"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624600"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/2.612254"},{"key":"ref7","first-page":"64","article-title":"PACT XPP: A Self-Reconfigurable Data Processing Architecture","volume-title":"Proc. 1st Int\u2019l Conf. Eng. of Reconfigurable Systems and Algorithms (ERSA)","author":"Baumgarte"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1023\/A:1024495400663","article-title":"Experience with a Hybrid Processor: K-Means Clustering","author":"Gokhale","year":"2003","journal-title":"J. Supercomputing"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624608"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/40.848473"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707878"},{"key":"ref12","first-page":"74","article-title":"Implementing High Speed Matrix Processing on a Reconfigurable Parallel Dataflow Processor","volume-title":"Proc. 2nd Int\u2019l Conf. Eng. of Reconfigurable Systems and Algorithms (ERSA)","author":"Gunnarsson"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903392"}],"container-title":["IEEE Micro"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/40\/22379\/01044300.pdf?arnumber=1044300","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,15]],"date-time":"2025-03-15T05:17:58Z","timestamp":1742015878000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1044300\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,9]]},"references-count":13,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2002,9]]}},"URL":"https:\/\/doi.org\/10.1109\/mm.2002.1044300","relation":{},"ISSN":["0272-1732"],"issn-type":[{"type":"print","value":"0272-1732"}],"subject":[],"published":{"date-parts":[[2002,9]]}}}