{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:06:38Z","timestamp":1763467598130,"version":"3.38.0"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2003,11,1]],"date-time":"2003-11-01T00:00:00Z","timestamp":1067644800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Micro"],"published-print":{"date-parts":[[2003,11]]},"DOI":"10.1109\/mm.2003.1261393","type":"journal-article","created":{"date-parts":[[2004,1,22]],"date-time":"2004-01-22T20:17:06Z","timestamp":1074802626000},"page":"99-107","source":"Crossref","is-referenced-by-count":64,"title":["Nonuniform cache architectures for wire-delay dominated on-chip caches"],"prefix":"10.1109","volume":"23","author":[{"family":"Changkyu Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Burger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.W.","family":"Keckler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"Analysis of Multi-Megabyte Secondary CPU Cache Memories","year":"1989","author":"Kessler","key":"refs1"},{"key":"refs2","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339660"},{"key":"refs3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1989.714547"},{"key":"refs4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991105"},{"key":"refs5","doi-asserted-by":"publisher","DOI":"10.1145\/106972.106980"},{"key":"refs6","doi-asserted-by":"publisher","DOI":"10.1145\/123465.123504"},{"key":"ref1","first-page":"171","article-title":"A 900-MHz 2.25-Mbyte Cache with On-Chip CPU Now in SOI\/Cu","volume-title":"Proc. IEEE Int\u2019l Solid-State Circuits Conf.","author":"Hill","year":"2001"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953300"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339691"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/2.612245"},{"key":"ref5","article-title":"Cacti 3.0: An Integrated Cache Timing, Power, and Area Model","volume-title":"tech. report","author":"Shivaku mar","year":"2001"},{"key":"ref6","article-title":"Sim-Alpha: A Validated Execution-Driven Alpha 21264 Simulator","volume-title":"tech. report TR 01-23","author":"Desikan","year":"2001"},{"year":"2001","key":"ref7","article-title":"Int\u2019l Technology Roadmap for Semiconductors"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1989.714547"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339660"},{"key":"ref11","first-page":"266","article-title":"An 833MHz 1.5w 18Mb CMOS SRAM with 1.67Gb\/s\/pin","volume-title":"Proc. 2000 IEEE Int\u2019l Solid-State Circuits Conf.","author":"Pilo","year":"2000"}],"container-title":["IEEE Micro"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/40\/28194\/01261393.pdf?arnumber=1261393","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,16]],"date-time":"2025-03-16T04:43:35Z","timestamp":1742100215000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1261393\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,11]]},"references-count":17,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2003,11]]}},"URL":"https:\/\/doi.org\/10.1109\/mm.2003.1261393","relation":{},"ISSN":["0272-1732"],"issn-type":[{"type":"print","value":"0272-1732"}],"subject":[],"published":{"date-parts":[[2003,11]]}}}