{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T17:42:56Z","timestamp":1769276576431,"version":"3.49.0"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,3,1]],"date-time":"2018-03-01T00:00:00Z","timestamp":1519862400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Micro"],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/mm.2018.022071133","type":"journal-article","created":{"date-parts":[[2018,4,20]],"date-time":"2018-04-20T18:05:39Z","timestamp":1524247539000},"page":"30-41","source":"Crossref","is-referenced-by-count":75,"title":["The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips"],"prefix":"10.1109","volume":"38","author":[{"given":"Scott","family":"Davidson","sequence":"first","affiliation":[{"name":"Bespoke Silicon Group, University of Washington"}]},{"given":"Shaolin","family":"Xie","sequence":"additional","affiliation":[{"name":"Bespoke Silicon Group, University of Washington"}]},{"given":"Christopher","family":"Torng","sequence":"additional","affiliation":[{"name":"Cornell University"}]},{"given":"Khalid","family":"Al-Hawai","sequence":"additional","affiliation":[{"name":"Cornell University"}]},{"given":"Austin","family":"Rovinski","sequence":"additional","affiliation":[{"name":"University of Michigan"}]},{"given":"Tutu","family":"Ajayi","sequence":"additional","affiliation":[{"name":"University of Michigan"}]},{"given":"Luis","family":"Vega","sequence":"additional","affiliation":[{"name":"Bespoke Silicon Group, University of Washington"}]},{"given":"Chun","family":"Zhao","sequence":"additional","affiliation":[{"name":"Bespoke Silicon Group, University of Washington"}]},{"given":"Ritchie","family":"Zhao","sequence":"additional","affiliation":[{"name":"Cornell University"}]},{"given":"Steve","family":"Dai","sequence":"additional","affiliation":[{"name":"Cornell University"}]},{"given":"Aporva","family":"Amarnath","sequence":"additional","affiliation":[{"name":"University of Michigan"}]},{"given":"Bandhav","family":"Veluri","sequence":"additional","affiliation":[{"name":"Bespoke Silicon Group, University of Washington"}]},{"given":"Paul","family":"Gao","sequence":"additional","affiliation":[{"name":"Bespoke Silicon Group, University of Washington"}]},{"given":"Anuj","family":"Rao","sequence":"additional","affiliation":[{"name":"Bespoke Silicon Group, University of Washington"}]},{"given":"Gai","family":"Liu","sequence":"additional","affiliation":[{"name":"Cornell University"}]},{"given":"Rajesh K.","family":"Gupta","sequence":"additional","affiliation":[{"name":"UC San Diego"}]},{"given":"Zhiru","family":"Zhang","sequence":"additional","affiliation":[{"name":"Cornell University"}]},{"given":"Ronald","family":"Dreslinski","sequence":"additional","affiliation":[{"name":"University of Michigan"}]},{"given":"Christopher","family":"Batten","sequence":"additional","affiliation":[{"name":"Cornell University"}]},{"given":"Michael Bedford","family":"Taylor","sequence":"additional","affiliation":[{"name":"Bespoke Silicon Group, University of Washington"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"ref3","year":"0","journal-title":"The rocket chip generator"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.11"},{"key":"ref6","year":"0","journal-title":"StreamIt"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11515-8_3"},{"key":"ref8","author":"courbariaux","year":"2016","journal-title":"Binarized neural networks Training deep neural networks with weights and activations constrained to +1 or ?1"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021741"},{"key":"ref2","author":"olofsson","year":"2008","journal-title":"Epiphany Architecture Reference Manual"},{"key":"ref9","article-title":"BaseJump STL: SystemVerilog Needs a Standard Template Library for Hardware Design","author":"taylor","year":"0","journal-title":"Design Automation Conference"},{"key":"ref1","article-title":"Celerity: An Open Source RISC-V Tiered Accelerator Fabric","author":"ajayi","year":"0","journal-title":"Hot Chips A Symposium on High Performance Chips"}],"container-title":["IEEE Micro"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/40\/8344464\/08344478.pdf?arnumber=8344478","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,4]],"date-time":"2022-05-04T19:50:27Z","timestamp":1651693827000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8344478\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":10,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/mm.2018.022071133","relation":{},"ISSN":["0272-1732","1937-4143"],"issn-type":[{"value":"0272-1732","type":"print"},{"value":"1937-4143","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,3]]}}}