{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,24]],"date-time":"2026-02-24T17:44:37Z","timestamp":1771955077161,"version":"3.50.1"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Micro"],"published-print":{"date-parts":[[2019,9,1]]},"DOI":"10.1109\/mm.2019.2931584","type":"journal-article","created":{"date-parts":[[2019,7,31]],"date-time":"2019-07-31T20:10:30Z","timestamp":1564603830000},"page":"102-111","source":"Crossref","is-referenced-by-count":21,"title":["DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator"],"prefix":"10.1109","volume":"39","author":[{"given":"Swagath","family":"Venkataramani","sequence":"first","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Jungwook","family":"Choi","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Vijayalakshmi","family":"Srinivasan","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Wei","family":"Wang","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Jintao","family":"Zhang","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Marcel","family":"Schaal","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Mauricio J.","family":"Serrano","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Kazuaki","family":"Ishizaki","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Hiroshi","family":"Inoue","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Eri","family":"Ogawa","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Moriyoshi","family":"Ohara","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Leland","family":"Chang","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]},{"given":"Kailash","family":"Gopalakrishnan","sequence":"additional","affiliation":[{"name":"IBM Research Labs"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00012"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080244"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.39"},{"key":"ref6","article-title":"Intel nGraph: An intermediate representation, compiler, and executor for deep learning","author":"cyphers","year":"2018"},{"key":"ref11","first-page":"1","article-title":"A compiler for deep neural network accelerators to generate optimized code for a wide range of data parameters from a hand-crafted computation kernel","author":"ogawa","year":"0","journal-title":"Proc IEEE Symposium on Low-Power and High-Speed Chips (Coolchips"},{"key":"ref5","first-page":"578","article-title":"TVM: an automated end-to-end optimizing compiler for deep learning","author":"chen","year":"0","journal-title":"Proc 12th USENIX Symp Operating Syst Des Implementation"},{"key":"ref8","first-page":"265","article-title":"TensorFlow: A system for large-scale machine learning","author":"abadi","year":"0","journal-title":"Proc 11th USENIX Conf Operating Syst Des Implementation"},{"key":"ref7","article-title":"Glow: Graph lowering compiler techniques for neural networks","author":"rotem","year":"2018"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502276"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"}],"container-title":["IEEE Micro"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/40\/8833530\/08782645.pdf?arnumber=8782645","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:07:48Z","timestamp":1657746468000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8782645\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,9,1]]},"references-count":11,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/mm.2019.2931584","relation":{},"ISSN":["0272-1732","1937-4143"],"issn-type":[{"value":"0272-1732","type":"print"},{"value":"1937-4143","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,9,1]]}}}