{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T02:28:05Z","timestamp":1767839285189,"version":"3.49.0"},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Micro"],"published-print":{"date-parts":[[2020,11,1]]},"DOI":"10.1109\/mm.2020.3012514","type":"journal-article","created":{"date-parts":[[2020,7,28]],"date-time":"2020-07-28T22:37:00Z","timestamp":1595975820000},"page":"59-66","source":"Crossref","is-referenced-by-count":5,"title":["Countering Load-to-Use Stalls in the NVIDIA Turing GPU"],"prefix":"10.1109","volume":"40","author":[{"given":"Ram","family":"Rangan","sequence":"first","affiliation":[{"name":"NVIDIA"}]},{"given":"Naman","family":"Turakhia","sequence":"additional","affiliation":[{"name":"NVIDIA"}]},{"given":"Alexandre","family":"Joly","sequence":"additional","affiliation":[{"name":"NVIDIA"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Structured buffer and byte address buffer","year":"0"},{"key":"ref3","article-title":"The peak-performance-percentage analysis method for optimizing any GPU workload","author":"bavoil","year":"2019"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485934"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.18"},{"key":"ref11","first-page":"5","article-title":"Radeon southern islands acceleration","year":"2012"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339685"},{"key":"ref12","article-title":"D3D12 Hardware Tiers","year":"0"},{"key":"ref8","article-title":"Identifying scalar behavior in CUDA kernels","year":"2011"},{"key":"ref7","article-title":"NVIDIA's next generation CUDA&#x2122;compute architecture: Fermi&#x2122;","year":"2009"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2019.8875651"},{"key":"ref9","first-page":"330","article-title":"Power-efficient computing for compute-intensive GPGPU applications","author":"gilani","year":"0","journal-title":"Proc Himachal Pradesh Cricket Assoc"},{"key":"ref1","article-title":"NVIDIA Turing GPU Architecture. Whitepaper number WP-09183-001_v01","year":"2018"}],"container-title":["IEEE Micro"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/40\/9234128\/09151311.pdf?arnumber=9151311","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,4]],"date-time":"2022-05-04T20:05:14Z","timestamp":1651694714000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9151311\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,1]]},"references-count":12,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/mm.2020.3012514","relation":{},"ISSN":["0272-1732","1937-4143"],"issn-type":[{"value":"0272-1732","type":"print"},{"value":"1937-4143","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,11,1]]}}}