{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,11]],"date-time":"2026-05-11T18:21:58Z","timestamp":1778523718434,"version":"3.51.4"},"reference-count":5,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2021,3,1]],"date-time":"2021-03-01T00:00:00Z","timestamp":1614556800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,3,1]],"date-time":"2021-03-01T00:00:00Z","timestamp":1614556800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,3,1]],"date-time":"2021-03-01T00:00:00Z","timestamp":1614556800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Micro"],"published-print":{"date-parts":[[2021,3,1]]},"DOI":"10.1109\/mm.2021.3061394","type":"journal-article","created":{"date-parts":[[2021,2,23]],"date-time":"2021-02-23T21:20:05Z","timestamp":1614115205000},"page":"29-35","source":"Crossref","is-referenced-by-count":339,"title":["NVIDIA A100 Tensor Core GPU: Performance and Innovation"],"prefix":"10.1109","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3282-6777","authenticated-orcid":false,"given":"Jack","family":"Choquette","sequence":"first","affiliation":[{"name":"NVIDIA, Singapore"}]},{"given":"Wishwesh","family":"Gandhi","sequence":"additional","affiliation":[{"name":"NVIDIA, Singapore"}]},{"given":"Olivier","family":"Giroux","sequence":"additional","affiliation":[{"name":"NVIDIA, Singapore"}]},{"given":"Nick","family":"Stam","sequence":"additional","affiliation":[{"name":"NVIDIA, Singapore"}]},{"given":"Ronny","family":"Krashinsky","sequence":"additional","affiliation":[{"name":"NVIDIA, Singapore"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1375527.1375568"},{"key":"ref3","article-title":"NVSwitch and DGX-2: NVLink-Switching chip and scale-up compute server","author":"ishii","year":"2018","journal-title":"Hot Chips"},{"key":"ref5","year":"0"},{"key":"ref2","article-title":"MLPerf training benchmark","author":"mattson","year":"2019"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.022071134"}],"container-title":["IEEE Micro"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/40\/9388768\/09361255.pdf?arnumber=9361255","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:56Z","timestamp":1652194256000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9361255\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,3,1]]},"references-count":5,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/mm.2021.3061394","relation":{},"ISSN":["0272-1732","1937-4143"],"issn-type":[{"value":"0272-1732","type":"print"},{"value":"1937-4143","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,3,1]]}}}