{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,2]],"date-time":"2024-07-02T21:13:29Z","timestamp":1719954809836},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Network"],"published-print":{"date-parts":[[2018,1]]},"DOI":"10.1109\/mnet.2018.1700141","type":"journal-article","created":{"date-parts":[[2018,1,26]],"date-time":"2018-01-26T19:16:20Z","timestamp":1516994180000},"page":"140-145","source":"Crossref","is-referenced-by-count":3,"title":["A Multi-Level Cache Framework for Remote Resource Access in Transparent Computing"],"prefix":"10.1109","volume":"32","author":[{"given":"Di","family":"Zhang","sequence":"first","affiliation":[]},{"given":"Yuezhi","family":"Zhou","sequence":"additional","affiliation":[]},{"given":"Yaoxue","family":"Zhang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MPRV.2009.82"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MNET.2017.1700030"},{"key":"ref12","first-page":"191","article-title":"Cache Write Policies and Performance","author":"jouppi","year":"0","journal-title":"Proc ISCA"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/35037.42183"},{"key":"ref14","first-page":"348","article-title":"A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories","author":"papamarcos","year":"0","journal-title":"Proc ISCA"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2519901"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-35795-4_82"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/319151.319153"},{"key":"ref5","first-page":"345","article-title":"On the Inclusion Properties for Multi-Level Cache Hierarchies","author":"baer","year":"0","journal-title":"Proc ISCA"},{"key":"ref8","article-title":"Mobile Edge Computing","author":"patel","year":"2012","journal-title":"ETSI White Paper"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2342509.2342513"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.comcom.2010.06.024"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/11833529_1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/cje.2016.11.016"}],"container-title":["IEEE Network"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/65\/8270616\/08270646.pdf?arnumber=8270646","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:19:07Z","timestamp":1642004347000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8270646\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1]]},"references-count":15,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/mnet.2018.1700141","relation":{},"ISSN":["0890-8044","1558-156X"],"issn-type":[{"value":"0890-8044","type":"print"},{"value":"1558-156X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,1]]}}}