{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T17:32:41Z","timestamp":1772645561064,"version":"3.50.1"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,5]]},"DOI":"10.1109\/mocast.2018.8376561","type":"proceedings-article","created":{"date-parts":[[2018,6,11]],"date-time":"2018-06-11T19:29:45Z","timestamp":1528745385000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Extending a 65nm CMOS process design kit for high total ionizing dose effects"],"prefix":"10.1109","author":[{"given":"Aristeidis","family":"Nikolaou","sequence":"first","affiliation":[]},{"given":"Matthias","family":"Bucher","sequence":"additional","affiliation":[]},{"given":"Nikos","family":"Makris","sequence":"additional","affiliation":[]},{"given":"Alexia","family":"Papadopoulou","sequence":"additional","affiliation":[]},{"given":"Loukas","family":"Chevas","sequence":"additional","affiliation":[]},{"given":"Giulio","family":"Borghello","sequence":"additional","affiliation":[]},{"given":"Henri D.","family":"Koch","sequence":"additional","affiliation":[]},{"given":"Kostas","family":"Kloukinas","sequence":"additional","affiliation":[]},{"given":"Tuomas S.","family":"Poikela","sequence":"additional","affiliation":[]},{"given":"Federico","family":"Faccio","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"166","article-title":"Total Ionizing Dose Effects on Analog Performance of 65 nm Bulk CMOS with Enclosed-Gate and Standard Layout","author":"bucher","year":"2018","journal-title":"IEEE Int Conf on Microelectronic Test Structure (ICMTS)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/S0168-9002(99)00899-2"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2492778"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2414426"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2164080"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2017.8066584"},{"key":"ref8","article-title":"BSIM4.5.0 MOSFET Model User's Manual","author":"xi","year":"2005","journal-title":"Dpt of EECS University of California Berkeley"},{"key":"ref7","first-page":"89","article-title":"Accurate BSIM4 MOS Model Extraction with Binning-Hybrid-Macro Methodology","author":"ching tan","year":"2016","journal-title":"IEEE Int Conf on Semiconductor Electronics (ICSE)"},{"key":"ref2","doi-asserted-by":"crossref","DOI":"10.1088\/1748-0221\/10\/05\/C05009","article-title":"1-Grad total dose evaluation of 65nm CMOS technology for the HL-LHC upgrades","volume":"10","author":"menouni","year":"2015","journal-title":"J Instrum"},{"key":"ref9","article-title":"EKV3 Compact MOSFET Model Documentation","author":"bazigos","year":"2008","journal-title":"Technical Report Technical University of Crete Greece"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2016.2646908"}],"event":{"name":"2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)","location":"Thessaloniki","start":{"date-parts":[[2018,5,7]]},"end":{"date-parts":[[2018,5,9]]}},"container-title":["2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8370368\/8376555\/08376561.pdf?arnumber=8376561","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,7,2]],"date-time":"2018-07-02T21:27:07Z","timestamp":1530566827000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8376561\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/mocast.2018.8376561","relation":{},"subject":[],"published":{"date-parts":[[2018,5]]}}}