{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:10:28Z","timestamp":1758892228353,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/mocast.2019.8741638","type":"proceedings-article","created":{"date-parts":[[2019,6,20]],"date-time":"2019-06-20T23:17:13Z","timestamp":1561072633000},"page":"1-4","source":"Crossref","is-referenced-by-count":6,"title":["Hardware Acceleration of SHA-256 Algorithm Using NIOS-II Processor"],"prefix":"10.1109","author":[{"given":"Argirios","family":"Sideris","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Theodora","family":"Sanida","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minas","family":"Dasygenis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.5815\/ijcnis.2015.01.02"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-005-0086-5"},{"journal-title":"Introduction to the Avalon Interface Specifications","year":"2018","key":"ref10"},{"journal-title":"FPGA Implementation of An HMAC Processor Based on the SHA-2 Family of Hash Functions","year":"2011","author":"juliato","key":"ref6"},{"journal-title":"Altera DE2–115 Development and Education Board","year":"0","author":"technologies","key":"ref11"},{"key":"ref5","first-page":"1","article-title":"Low power and simple implementation of Secure Hashing Algorithm (SHA-2) using VHDL Implemented on FPGA of SHA-224\/256 Core","volume":"8","author":"thakur","year":"2018","journal-title":"International Journal of Engineering and Management Research (IJEMR)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ESTMED.2005.1518073"},{"journal-title":"Nios II Processors for FPGAs - Intel FPGA","year":"0","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/NSWCTC.2010.131"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2010.5575173"},{"journal-title":"Secure Hash Standard (SHS)","year":"2018","author":"dang","key":"ref1"}],"event":{"name":"2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST)","start":{"date-parts":[[2019,5,13]]},"location":"Thessaloniki, Greece","end":{"date-parts":[[2019,5,15]]}},"container-title":["2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8732971\/8741537\/08741638.pdf?arnumber=8741638","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T16:26:15Z","timestamp":1658247975000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8741638\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/mocast.2019.8741638","relation":{},"subject":[],"published":{"date-parts":[[2019,5]]}}}