{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,11,19]],"date-time":"2024-11-19T16:31:36Z","timestamp":1732033896914},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/mse.2011.5937102","type":"proceedings-article","created":{"date-parts":[[2011,7,7]],"date-time":"2011-07-07T17:27:57Z","timestamp":1310059677000},"page":"94-97","source":"Crossref","is-referenced-by-count":1,"title":["VEasy: A tool suite for teaching VLSI functional verification"],"prefix":"10.1109","author":[{"given":"Samuel Nascimento","family":"Pagliarini","sequence":"first","affiliation":[]},{"given":"Fernanda Lima","family":"Kastensmidt","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"VEasy-a Functional Verification Tool Suite","year":"2010","author":"pagliarini","key":"ref10"},{"journal-title":"Principles of Verifiable RTL Design a Functional Coding Style Supporting Verification Processes in Verilog","year":"0","author":"bening","key":"ref11"},{"journal-title":"Standard Verilog Hardware Description Language","year":"2001","key":"ref12"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"454","DOI":"10.1145\/196244.196467","article-title":"hsis: a bdd-based environment for formal verification","author":"aziz","year":"1994","journal-title":"31st Design Automation Conference"},{"journal-title":"Standard for the Property Specification Language (PSL)","year":"2005","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397275"},{"key":"ref6","first-page":"158","article-title":"User defined coverage-a tool supported methodology for design verication","author":"grinwald","year":"1998","journal-title":"Proc 35th Annual Design Automation Conference"},{"journal-title":"Standard for SystemVerilog-Unified Hardware Design Specification and Verification Language","year":"2009","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775907"},{"journal-title":"Verification Methodology Manual Techniques for Verifying HDL Designs","year":"2001","author":"dempster","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1999.810715"},{"journal-title":"Functional Verification Coverage Measurement and Analysis","year":"2004","author":"piziali","key":"ref1"},{"journal-title":"Design for verification methodology allows silicon success","year":"2003","author":"schutten","key":"ref9"}],"event":{"name":"2011 IEEE International Conference on Microelectronic Systems Education (MSE)","start":{"date-parts":[[2011,6,5]]},"location":"San Diego, CA, USA","end":{"date-parts":[[2011,6,6]]}},"container-title":["2011 IEEE International Conference on Microelectronic Systems Education"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5899296\/5937069\/05937102.pdf?arnumber=5937102","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T02:56:48Z","timestamp":1497927408000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5937102\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/mse.2011.5937102","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}