{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T10:27:32Z","timestamp":1730284052580,"version":"3.28.0"},"reference-count":2,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/mtdt.2002.1029768","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T22:14:31Z","timestamp":1056579271000},"page":"88-91","source":"Crossref","is-referenced-by-count":0,"title":["Adder merged DRAM architecture"],"prefix":"10.1109","author":[{"given":"M.","family":"Hashimoto","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref2","first-page":"74","article-title":"A 4-Level Storage 4Gb DRAM","author":"murotani","year":"0","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref1","first-page":"125","article-title":"A DRAM Based Functional Memory for Addition","volume":"97?95","author":"yamaoka","year":"1997","journal-title":"IEICE Tech Report"}],"event":{"name":"Records of the 2002 IEEE International Workshop on Memory Technology, Design and Testing","acronym":"MTDT-02","location":"Isle of Bendor, France"},"container-title":["Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8004\/22126\/01029768.pdf?arnumber=1029768","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,10]],"date-time":"2017-03-10T21:26:23Z","timestamp":1489181183000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1029768\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":2,"URL":"https:\/\/doi.org\/10.1109\/mtdt.2002.1029768","relation":{},"subject":[]}}