{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,14]],"date-time":"2025-10-14T06:47:56Z","timestamp":1760424476088},"reference-count":15,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/mtdt.2002.1029771","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T18:14:31Z","timestamp":1056564871000},"page":"109-116","source":"Crossref","is-referenced-by-count":5,"title":["A fault modeling technique to test memory BIST algorithms"],"prefix":"10.1109","author":[{"given":"R.","family":"Venkatesh","sequence":"first","affiliation":[]},{"given":"S.","family":"Kumar","sequence":"additional","affiliation":[]},{"given":"J.","family":"Philip","sequence":"additional","affiliation":[]},{"given":"S.","family":"Shukla","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"675","article-title":"An Algorithm to test RAMS for Physical Neighborhood Pattern Sensitive Faults","author":"manoj","year":"0","journal-title":"IEEE International Test Conference"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.986429"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1993.470620"},{"journal-title":"Fault Modeling and Test Algorithm Development for Static Random Access Memories","year":"0","author":"dekker","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.55188"},{"journal-title":"Fault Models and Tests for Coupling Faults in Random-Access Memories","year":"1990","author":"cockburn","key":"ref15"},{"journal-title":"User Manual","article-title":"TSMC 0.13mm Process High-Speed Dual-Port SRAM (HS-DPRAM-SP) Generator","year":"0","key":"ref4"},{"journal-title":"User Manual","article-title":"TSMC 0.13mm Process High-Speed Single-Port SRAM (HS-SRAM-SP) Generator","year":"0","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/54.573357"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1999.761206"},{"journal-title":"Testing Semiconductor Memories","year":"1991","author":"van de goor","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1997.573351"},{"journal-title":"Built-In Self-Test Process Guide Mentor Graphics","year":"0","key":"ref2"},{"journal-title":"The STAR Memory System Virage Logic Systems","article-title":"The First Complete Embedded Self Test And Repair Memory System for SOC Applications","year":"0","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/41.19076"}],"event":{"name":"Records of the 2002 IEEE International Workshop on Memory Technology, Design and Testing","acronym":"MTDT-02","location":"Isle of Bendor, France"},"container-title":["Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8004\/22126\/01029771.pdf?arnumber=1029771","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,10]],"date-time":"2017-03-10T16:22:28Z","timestamp":1489162948000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1029771\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/mtdt.2002.1029771","relation":{},"subject":[]}}