{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:50:09Z","timestamp":1729615809888,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/mtv.2003.1250261","type":"proceedings-article","created":{"date-parts":[[2004,5,6]],"date-time":"2004-05-06T20:18:03Z","timestamp":1083874683000},"page":"38-43","source":"Crossref","is-referenced-by-count":0,"title":["Utilizing various ADL facets for instruction level CPU test"],"prefix":"10.1109","author":[{"given":"E.","family":"Safi","sequence":"first","affiliation":[]},{"given":"Z.","family":"Karimi","sequence":"additional","affiliation":[]},{"given":"M.","family":"Abbaspour","sequence":"additional","affiliation":[]},{"given":"Z.","family":"Navabi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766644"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915026"},{"article-title":"IP-Based Application Specific Instruction-set Processor Design","year":"2003","author":"abbaspour","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998361"},{"key":"ref11","first-page":"331","article-title":"Retargetable Binary Utilities","author":"abbaspour","year":"2002","journal-title":"ACM IEEE Design Automation Conference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1018130"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253691"},{"article-title":"Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV","year":"2002","author":"mishra","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675602"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"369","DOI":"10.1109\/43.913755","article-title":"Software-Based Self-Testing Methodology for Processor Cores","volume":"20","author":"li","year":"2001","journal-title":"IEEE Transaction on CAD of Integrated Circuits and Systems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/307418.307549"},{"key":"ref1","first-page":"990","article-title":"Native mode functional test generation for processors with applications to self test and design validation","author":"shen","year":"1998","journal-title":"International Test Conference"}],"event":{"name":"4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions","acronym":"MTV-03","location":"Austin, TX, USA"},"container-title":["Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8841\/27975\/01250261.pdf?arnumber=1250261","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T06:52:22Z","timestamp":1497595942000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1250261\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/mtv.2003.1250261","relation":{},"subject":[]}}