{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:46:00Z","timestamp":1729622760888,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,8]]},"DOI":"10.1109\/mwscas.2013.6674590","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T16:14:10Z","timestamp":1386173650000},"page":"81-84","source":"Crossref","is-referenced-by-count":0,"title":["Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells"],"prefix":"10.1109","author":[{"given":"E.","family":"Amat","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.G.","family":"Almudever","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Aymerich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Rubio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Canal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1877745.1877746"},{"key":"14","doi-asserted-by":"crossref","first-page":"1433","DOI":"10.1109\/JSSC.1989.572629","article-title":"Matching properties of MOS transistors","volume":"24","author":"pelgrom","year":"1989","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.898683"},{"key":"12","first-page":"734","article-title":"Low-leakage SRAM design with dual Vt transistors","author":"amelifard","year":"2006","journal-title":"IEEE Int Symp Quality Electronic Design"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2009633"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0339"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228414"},{"key":"10","first-page":"103","article-title":"Variability mitigation mechanisms in scaled 3T1D DRAM memories to 22nm and beyond","volume":"13","author":"amat","year":"2013","journal-title":"IEEE TDMR"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705371"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2009.5318794"},{"key":"5","first-page":"118","article-title":"Comprehensive analysis of variability sources of FinFET characteristics","author":"matsukawa","year":"2009","journal-title":"Symposium on VLSI Technology"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2006.251056"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2009.5413124"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.12"}],"event":{"name":"2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)","start":{"date-parts":[[2013,8,4]]},"location":"Columbus, OH, USA","end":{"date-parts":[[2013,8,7]]}},"container-title":["2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6653322\/6674559\/06674590.pdf?arnumber=6674590","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T23:39:42Z","timestamp":1498088382000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6674590\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,8]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/mwscas.2013.6674590","relation":{},"subject":[],"published":{"date-parts":[[2013,8]]}}}