{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:16:40Z","timestamp":1729621000088,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1109\/mwscas.2014.6908342","type":"proceedings-article","created":{"date-parts":[[2014,9,30]],"date-time":"2014-09-30T10:54:51Z","timestamp":1412074491000},"page":"21-24","source":"Crossref","is-referenced-by-count":1,"title":["Process variation verification of low-power secure CSSAL AES S-box circuit"],"prefix":"10.1109","author":[{"given":"Cancio","family":"Monteiro","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yasuhiro","family":"Takahashi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toshikazu","family":"Sekine","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"crossref","DOI":"10.6028\/NIST.FIPS.197","author":"national institute of standards and technology (nist)","year":"2001","journal-title":"The advanced encryption standard (aes)"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/WAC.2006.375739"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.10.0209.0247"},{"key":"1","first-page":"388","article-title":"Differential power analysis","author":"kocher","year":"1999","journal-title":"Proc Int Adv in Cryptol Conf (CRYPTO)"},{"key":"7","first-page":"232","article-title":"Three-phase dual-rail pre-charge logic","author":"bucci","year":"2006","journal-title":"Proc CHES'06"},{"key":"6","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","author":"tiri","year":"2002","journal-title":"Proceedings of the 28th European Solid-State Circuits Conference ESSCIRC"},{"key":"5","first-page":"172","article-title":"An optimized S-box circuit architecture for low power AES design","volume":"2523","author":"morioka","year":"2003","journal-title":"Proc 4th Int Workshop on CHES 2002 LNCS"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2011.6026559"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/92.335009"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2013.04.003"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224115"}],"event":{"name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","start":{"date-parts":[[2014,8,3]]},"location":"College Station, TX, USA","end":{"date-parts":[[2014,8,6]]}},"container-title":["2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6900043\/6908326\/06908342.pdf?arnumber=6908342","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,15]],"date-time":"2019-08-15T13:06:32Z","timestamp":1565874392000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6908342\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/mwscas.2014.6908342","relation":{},"subject":[],"published":{"date-parts":[[2014,8]]}}}