{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T10:27:58Z","timestamp":1730284078425,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1109\/mwscas.2014.6908393","type":"proceedings-article","created":{"date-parts":[[2014,9,30]],"date-time":"2014-09-30T10:54:51Z","timestamp":1412074491000},"page":"226-229","source":"Crossref","is-referenced-by-count":1,"title":["Average placement method with common centroid constraints for analog IC layout design"],"prefix":"10.1109","author":[{"given":"Kunihiro","family":"Fujiyoshi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keitaro","family":"Ue","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E97.A.339"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2006.342204"},{"key":"14","first-page":"1","article-title":"The improvement of rectilinear block packing using sequence-pair","author":"machida","year":"2001","journal-title":"IEICE Technical Report VLD2000-134"},{"key":"11","first-page":"31","article-title":"On handling cell placement with adjacent symmetry constraints for analog IC layout design","author":"koda","year":"2006","journal-title":"IEICE Technical Report VLD2006-77"},{"key":"12","first-page":"3148","article-title":"An improved method of convex rectilinear block packing based on sequence-pair","volume":"e86 a","author":"wakata","year":"2003","journal-title":"IEICE Trans Fundamentals"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1993.693094"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052250"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/4.284714"},{"key":"10","first-page":"8","article-title":"Corner block list: An effective and efficient topological representation of non-slicing floorplan","author":"hong","year":"2000","journal-title":"Proc ICCAD"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796506"},{"key":"6","first-page":"579","article-title":"Analog placement with common centroid constraints","author":"ma","year":"2007","journal-title":"Proc ICCAD"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024847"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681591"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.480159"},{"key":"8","first-page":"334","article-title":"A method of analog IC placement with common centroid constraints","author":"ue","year":"2012","journal-title":"Proc SASIMI"}],"event":{"name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","start":{"date-parts":[[2014,8,3]]},"location":"College Station, TX, USA","end":{"date-parts":[[2014,8,6]]}},"container-title":["2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6900043\/6908326\/06908393.pdf?arnumber=6908393","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T15:28:14Z","timestamp":1490282894000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6908393\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/mwscas.2014.6908393","relation":{},"subject":[],"published":{"date-parts":[[2014,8]]}}}