{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:41:53Z","timestamp":1729662113183,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1109\/mwscas.2014.6908397","type":"proceedings-article","created":{"date-parts":[[2014,9,30]],"date-time":"2014-09-30T10:54:51Z","timestamp":1412074491000},"page":"242-245","source":"Crossref","is-referenced-by-count":0,"title":["Low-power loop pipelining mapping onto CGRA utilizing variable dual V&lt;inf&gt;DD&lt;\/inf&gt;"],"prefix":"10.1109","author":[{"given":"Bing","family":"Xu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shouyi","family":"Yin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leibo","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaojun","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"crossref","first-page":"310","DOI":"10.1145\/1165573.1165646","article-title":"Power-conscious configuration cache structure and code mapping for coarsegrained reconfigurable architecture","author":"kim","year":"2006","journal-title":"Proc of the 2006 International Symposium on Low Power Electronics and Design"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-45234-8_7","article-title":"ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix","author":"mei","year":"2003","journal-title":"Proc 15th Int Conf Field Programmable Logic Applicat"},{"key":"10","article-title":"A fast application-based supply voltage optimization method for dual voltage FPGA","author":"zhu","year":"2013","journal-title":"IEEE Transaction on Very Large Scale Integration Systems"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228600"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454140"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2007.4439291"},{"key":"4","doi-asserted-by":"crossref","first-page":"136","DOI":"10.1145\/1176760.1176778","article-title":"Modulo graph embedding: Mapping applications onto coarse-grained reconfigurable architectures","author":"park","year":"2006","journal-title":"Proc of the 2006 International Conference on Compilers Architecture and Synthesis for Embedded Systems"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488757"},{"key":"8","article-title":"Low-power reconfigrable processor utilizing variable dual vdd","volume":"60","author":"zhu","year":"2013","journal-title":"IEEE Transaction on Circuits and Systems-II Express Briefs"}],"event":{"name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","start":{"date-parts":[[2014,8,3]]},"location":"College Station, TX, USA","end":{"date-parts":[[2014,8,6]]}},"container-title":["2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6900043\/6908326\/06908397.pdf?arnumber=6908397","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,15]],"date-time":"2019-08-15T13:06:36Z","timestamp":1565874396000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6908397\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/mwscas.2014.6908397","relation":{},"subject":[],"published":{"date-parts":[[2014,8]]}}}