{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T17:41:20Z","timestamp":1772905280790,"version":"3.50.1"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1109\/mwscas.2014.6908466","type":"proceedings-article","created":{"date-parts":[[2014,9,30]],"date-time":"2014-09-30T10:54:51Z","timestamp":1412074491000},"page":"519-522","source":"Crossref","is-referenced-by-count":5,"title":["Efficient and accurate RIE modeling methodology for BEOL 2.5D parasitic extraction"],"prefix":"10.1109","author":[{"given":"Nur Kurt","family":"Karsilayan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jim","family":"Falbo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dusan","family":"Petranovic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"Modeling of 65nm & 45nm manufacturing effects in Cadence QRC extractor & impact on timing analysis","author":"rangarajan","year":"2007","journal-title":"Cadence Designer Network"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127914"},{"key":"1","year":"0","journal-title":"The International Technology Roadmap for Semiconductors"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.828111"},{"key":"6","article-title":"Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects","volume":"9","author":"jin","year":"2001","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/43.486272"},{"key":"4","author":"abrokwah","year":"2006","journal-title":"Characterization and Modeling of Plasma Etch Pattern Dependencies in Integrated Circuits"}],"event":{"name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","location":"College Station, TX, USA","start":{"date-parts":[[2014,8,3]]},"end":{"date-parts":[[2014,8,6]]}},"container-title":["2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6900043\/6908326\/06908466.pdf?arnumber=6908466","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T11:59:07Z","timestamp":1602676747000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6908466"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/mwscas.2014.6908466","relation":{},"subject":[],"published":{"date-parts":[[2014,8]]}}}