{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T16:14:22Z","timestamp":1725725662884},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/mwscas.2016.7869952","type":"proceedings-article","created":{"date-parts":[[2017,3,7]],"date-time":"2017-03-07T19:33:58Z","timestamp":1488915238000},"page":"1-4","source":"Crossref","is-referenced-by-count":5,"title":["FinFET MPSoC 32 Gb\/s transceivers: Custom ESD protection and verification"],"prefix":"10.1109","author":[{"given":"James","family":"Karp","sequence":"first","affiliation":[]},{"given":"Michael J.","family":"Hart","sequence":"additional","affiliation":[]},{"given":"Mohammed","family":"Fakhruddin","sequence":"additional","affiliation":[]},{"given":"Vassili","family":"Kireev","sequence":"additional","affiliation":[]},{"given":"Larry","family":"Horwitz","sequence":"additional","affiliation":[]},{"given":"Matthew","family":"Hogan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Verification Methodology for Custom ESD PDK","author":"fakhruddin","year":"2016","journal-title":"Mentor Graphics"},{"year":"2011","author":"lo","article-title":"Method and apparatus for evaluating paths in an integrated circuit design","key":"ref11"},{"year":"2009","journal-title":"White Paper 2 A case for lowering component level CDM ESD specifications and requirements","first-page":"33","key":"ref12"},{"key":"ref13","first-page":"4c.5.1","article-title":"Intrinsic transistor reliability improvements from 22nm tri-gate technology","author":"ramey","year":"2013","journal-title":"IEEE IRPS"},{"year":"2015","author":"karp","article-title":"Circuit for and method of enabling the discharge of electric charge in an integrated circuit","key":"ref4"},{"key":"ref3","first-page":"1","article-title":"Effect of flip-chip package parameters on CDM discharge","author":"karp","year":"0"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/JSSC.2003.818568"},{"year":"2014","author":"karp","article-title":"Cell-level electrostatic discharge protection for an integrated circuit","key":"ref5"},{"year":"2012","author":"kireev","article-title":"T-coil network design for improved bandwidth and electrostatic discharge immunity","key":"ref8"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/ECTC.2007.373789"},{"year":"2002","author":"wang","journal-title":"On-Chip ESD Protection for Integrated Circuits An IC Design Perspective","key":"ref2"},{"year":"2016","journal-title":"16nm FinFET Virtex UltraScale+ FPGA The GTY SerDes are running at 32 75 Gbps","key":"ref1"},{"year":"0","journal-title":"Calibre &#x00AE; PERC&#x2122;","key":"ref9"}],"event":{"name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","start":{"date-parts":[[2016,10,16]]},"location":"Abu Dhabi, United Arab Emirates","end":{"date-parts":[[2016,10,19]]}},"container-title":["2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7862453\/7869936\/07869952.pdf?arnumber=7869952","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,11]],"date-time":"2017-03-11T02:37:38Z","timestamp":1489199858000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7869952\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/mwscas.2016.7869952","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}