{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T09:18:41Z","timestamp":1773825521027,"version":"3.50.1"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,8,1]],"date-time":"2019-08-01T00:00:00Z","timestamp":1564617600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,8,1]],"date-time":"2019-08-01T00:00:00Z","timestamp":1564617600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,8,1]],"date-time":"2019-08-01T00:00:00Z","timestamp":1564617600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,8]]},"DOI":"10.1109\/mwscas.2019.8885195","type":"proceedings-article","created":{"date-parts":[[2019,10,31]],"date-time":"2019-10-31T19:44:38Z","timestamp":1572551078000},"page":"762-765","source":"Crossref","is-referenced-by-count":3,"title":["An 8-b 2b\/cycle Asynchronous SAR ADC with Capacitive Divider Based RC-DAC"],"prefix":"10.1109","author":[{"given":"Jiu","family":"Xiong","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiajun","family":"Ren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243803"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"1829","DOI":"10.1109\/TCSI.2009.2037403","article-title":"An Asynchronous Binary-Search ADC Architecture with a Reduced Comparator Count","volume":"57","author":"lin","year":"2010","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2190117"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2333679"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1109\/TCSII.2018.2833866","article-title":"A 10-Bit 5 MS\/s VCOSAR ADC in 0.18-um CMOS","volume":"66","author":"xie","year":"2019","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560283"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2214181"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1763","DOI":"10.1109\/TVLSI.2018.2832472","article-title":"A LowPower Pipelined-SAR ADC using Boosted Bucket-Brigade Device for Residue Charge Processing","volume":"26","author":"zhang","year":"2018","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2012329"}],"event":{"name":"2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)","location":"Dallas, TX, USA","start":{"date-parts":[[2019,8,4]]},"end":{"date-parts":[[2019,8,7]]}},"container-title":["2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8882388\/8884793\/08885195.pdf?arnumber=8885195","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,17]],"date-time":"2022-07-17T17:55:36Z","timestamp":1658080536000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8885195\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,8]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/mwscas.2019.8885195","relation":{},"subject":[],"published":{"date-parts":[[2019,8]]}}}