{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:16:33Z","timestamp":1766067393054,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,8,9]],"date-time":"2021-08-09T00:00:00Z","timestamp":1628467200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,8,9]],"date-time":"2021-08-09T00:00:00Z","timestamp":1628467200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,8,9]],"date-time":"2021-08-09T00:00:00Z","timestamp":1628467200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,8,9]]},"DOI":"10.1109\/mwscas47672.2021.9531835","type":"proceedings-article","created":{"date-parts":[[2021,9,13]],"date-time":"2021-09-13T18:17:52Z","timestamp":1631557072000},"page":"812-815","source":"Crossref","is-referenced-by-count":6,"title":["A Novel Architecture for Memristor-Based Logic"],"prefix":"10.1109","author":[{"given":"Farzad","family":"Mozafari","sequence":"first","affiliation":[]},{"given":"Mohammad","family":"Javad Sharifi","sequence":"additional","affiliation":[]},{"given":"Arash","family":"Ahmadi","sequence":"additional","affiliation":[]},{"given":"Majid","family":"Ahmadi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.12.006"},{"article-title":"Reliable SPICE simulations of memristors, memcapacitors and meminductors","year":"2013","author":"biolek","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-10-7901-6_6"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2016.2547842"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2809644"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2011.2166369"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2699679"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"895","DOI":"10.1109\/TCSII.2014.2357292","article-title":"MAGIC—Memristor-aided logic","volume":"61","author":"kvatinsky","year":"2014","journal-title":"IEEE Transactions on Circuits and Systems II Express Briefs"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1038\/nature08940"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2016.2583673"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref9","first-page":"1","article-title":"MRL—Memristor ratioed logic","author":"kvatinsky","year":"2012","journal-title":"Cellular Nanoscale Networks and Their Applications (CNNA) 2013 12th International Workshop on"}],"event":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","start":{"date-parts":[[2021,8,9]]},"location":"Lansing, MI, USA","end":{"date-parts":[[2021,8,11]]}},"container-title":["2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9531648\/9531647\/09531835.pdf?arnumber=9531835","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T11:45:44Z","timestamp":1652183144000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9531835\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,8,9]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/mwscas47672.2021.9531835","relation":{},"subject":[],"published":{"date-parts":[[2021,8,9]]}}}