{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,31]],"date-time":"2024-08-31T05:51:57Z","timestamp":1725083517301},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,8]]},"DOI":"10.1109\/mwscas48704.2020.9184603","type":"proceedings-article","created":{"date-parts":[[2020,9,2]],"date-time":"2020-09-02T20:53:58Z","timestamp":1599080038000},"source":"Crossref","is-referenced-by-count":2,"title":["Formal Verification of Completion-Completeness for NCL Circuits"],"prefix":"10.1109","author":[{"given":"Son N.","family":"Le","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudarshan K.","family":"Srinivasan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Scott C.","family":"Smith","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.2200\/S00202ED1V01Y200907DCS023"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(01)00013-X"},{"key":"ref6","first-page":"143","article-title":"Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-wise Completion Strategy","author":"smith","year":"2003","journal-title":"International Conference on VLSI"},{"key":"ref5","first-page":"218","article-title":"System Timing","author":"seitz","year":"1980","journal-title":"Introduction to VLSI Systems"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-45641-6_26"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/PBCS061E_ch15"},{"key":"ref2","first-page":"663","article-title":"Asynchronous Digital Circuits","author":"di","year":"2012","journal-title":"Extreme Environment Electronics"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78800-3_24"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"261","DOI":"10.1109\/ASAP.1996.542821","article-title":"NULL Convention Logic: A Complete and Consistent Logic for Asynchronous Digital Circuit Synthesis","author":"fant","year":"1996","journal-title":"International Conference on Application Specific Systems Architectures and Processors"}],"event":{"name":"2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)","location":"Springfield, MA, USA","start":{"date-parts":[[2020,8,9]]},"end":{"date-parts":[[2020,8,12]]}},"container-title":["2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9178719\/9184428\/09184603.pdf?arnumber=9184603","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T21:53:28Z","timestamp":1656453208000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9184603\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/mwscas48704.2020.9184603","relation":{},"subject":[],"published":{"date-parts":[[2020,8]]}}}