{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,16]],"date-time":"2025-05-16T06:47:58Z","timestamp":1747378078722},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,8]]},"DOI":"10.1109\/mwscas48704.2020.9184614","type":"proceedings-article","created":{"date-parts":[[2020,9,2]],"date-time":"2020-09-02T16:53:58Z","timestamp":1599065638000},"page":"85-88","source":"Crossref","is-referenced-by-count":2,"title":["Implementation of Multi Spin-Thread Architecture to Fully-Connected Annealing Processing AI Chips"],"prefix":"10.1109","author":[{"given":"Ryoma","family":"Iimura","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satoshi","family":"Kitamura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takayuki","family":"Kawahara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2016.7604797"},{"key":"ref3","article-title":"A 2&#x00D7;30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In Memory Approach for Solving Large-Scale Combinatorial Optimization Problems","author":"takemoto","year":"2019","journal-title":"ISSCC 2019"},{"key":"ref6","article-title":"STATICA: A 512-Spin 0.25M-Weight FullDigital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions","author":"yamamoto","year":"2020","journal-title":"ISSCC 2020"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SAMI48414.2020.9108766"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2019.8885105"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063111"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1287\/opre.36.3.493"}],"event":{"name":"2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)","start":{"date-parts":[[2020,8,9]]},"location":"Springfield, MA, USA","end":{"date-parts":[[2020,8,12]]}},"container-title":["2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9178719\/9184428\/09184614.pdf?arnumber=9184614","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T17:58:28Z","timestamp":1656439108000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9184614\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/mwscas48704.2020.9184614","relation":{},"subject":[],"published":{"date-parts":[[2020,8]]}}}