{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,4]],"date-time":"2025-09-04T14:10:56Z","timestamp":1756995056197},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,8]]},"DOI":"10.1109\/mwscas48704.2020.9184647","type":"proceedings-article","created":{"date-parts":[[2020,9,2]],"date-time":"2020-09-02T20:53:58Z","timestamp":1599080038000},"page":"814-817","source":"Crossref","is-referenced-by-count":3,"title":["Single Wire Debug Interface"],"prefix":"10.1109","author":[{"given":"Bhanu","family":"Singh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sharath","family":"Patil","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"RealView ICE and RealView Trace Version 3 1 User-Guide","year":"0","key":"ref4"},{"journal-title":"Multi-ICE User Guide Version 2 2","year":"0","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297619"},{"key":"ref6","article-title":"Roadmaps of Packaging Technology","author":"bogatin","year":"1997","journal-title":"Integrated Circuit Engineering"},{"article-title":"Serial Wire Debug and the CoreSight Debug and TraceArchitecture","year":"2001","author":"ash_eld","key":"ref11"},{"journal-title":"How does the JTAG synchronization logic work?","year":"0","key":"ref5"},{"article-title":"Low Pin-count Debug Interfaces for Multi-device Systems","year":"0","author":"williams","key":"ref12"},{"article-title":"Technical Report: CVEL-07-001 An Overview of Advanced Electronic Packaging Technology","year":"2007","author":"kwak","key":"ref8"},{"journal-title":"Fundamentals of Microsystems Packaging","year":"2001","author":"tummala","key":"ref7"},{"year":"0","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355572"},{"journal-title":"IEEE Std 1149 1-2001","article-title":"Standard Test Access Port and Boundary-scan Architecture","year":"2001","key":"ref1"}],"event":{"name":"2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)","start":{"date-parts":[[2020,8,9]]},"location":"Springfield, MA, USA","end":{"date-parts":[[2020,8,12]]}},"container-title":["2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9178719\/9184428\/09184647.pdf?arnumber=9184647","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T21:56:39Z","timestamp":1656453399000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9184647\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/mwscas48704.2020.9184647","relation":{},"subject":[],"published":{"date-parts":[[2020,8]]}}}