{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T19:05:01Z","timestamp":1775070301435,"version":"3.50.1"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,8]]},"DOI":"10.1109\/mwscas48704.2020.9184662","type":"proceedings-article","created":{"date-parts":[[2020,9,2]],"date-time":"2020-09-02T20:53:58Z","timestamp":1599080038000},"page":"505-508","source":"Crossref","is-referenced-by-count":10,"title":["A Reversible-Logic based Architecture for Artificial Neural Network"],"prefix":"10.1109","author":[{"given":"Bappaditya","family":"Dey","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kasem","family":"Khalil","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ashok","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Magdy","family":"Bayoumi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3010743"},{"key":"ref11","author":"goodfellow","year":"2016","journal-title":"Deep Learning"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2018.8617887"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2019.8884809"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2004.1434722"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2015.08.137"},{"key":"ref16","article-title":"An introduction to spiking neural networks: Probabilistic models, learning rules, and applications","author":"jang","year":"2018"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2017.00123"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2015.11.017"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2004.1381072"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/rd.176.0525"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/rd.53.0183"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2020.2995784"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2019.8885015"},{"key":"ref8","first-page":"5","article-title":"Introduction to reversible logic gates & its application","author":"yelekar","year":"2011","journal-title":"2nd National Conference on Information and Communication Technology"},{"key":"ref7","first-page":"57","article-title":"Efficient approaches for designing quantum costs of various reversible gates","volume":"9","author":"surekha","year":"2017","journal-title":"International journal of engineering"},{"key":"ref2","first-page":"417","article-title":"A review on reversible logic gates and their implementation","volume":"3","author":"garipelly","year":"2013","journal-title":"International Journal of Emerging Technology and Advanced Engineering"},{"key":"ref9","article-title":"Hardware implementation of artificial neural networks","author":"forssell","year":"2014"},{"key":"ref1","article-title":"Cramming more components onto integrated circuits","author":"moore","year":"1965"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC46988.2019.1570548351"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/NETACT.2017.8076746"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2004.1399185"},{"key":"ref24","first-page":"571","article-title":"Implementation of programmable digital sigmoid function circuit for neuro-computing","author":"al-nsour","year":"1998","journal-title":"1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2016.7869646"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICSPS.2009.166"}],"event":{"name":"2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)","location":"Springfield, MA, USA","start":{"date-parts":[[2020,8,9]]},"end":{"date-parts":[[2020,8,12]]}},"container-title":["2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9178719\/9184428\/09184662.pdf?arnumber=9184662","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T21:53:07Z","timestamp":1656453187000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9184662\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/mwscas48704.2020.9184662","relation":{},"subject":[],"published":{"date-parts":[[2020,8]]}}}