{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,20]],"date-time":"2026-03-20T00:06:53Z","timestamp":1773965213837,"version":"3.50.1"},"reference-count":27,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,8,6]],"date-time":"2023-08-06T00:00:00Z","timestamp":1691280000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,8,6]],"date-time":"2023-08-06T00:00:00Z","timestamp":1691280000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100014553","name":"Samsung Advanced Institute of Technology (SAIT)","doi-asserted-by":"publisher","award":["10230223-05124-01"],"award-info":[{"award-number":["10230223-05124-01"]}],"id":[{"id":"10.13039\/100014553","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea (NRF)","doi-asserted-by":"publisher","award":["2021-R1A2C2008864"],"award-info":[{"award-number":["2021-R1A2C2008864"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100008122","name":"Institute of Information and communications Technology Planning and Evaluation (IITP)","doi-asserted-by":"publisher","award":["2021-0-00754"],"award-info":[{"award-number":["2021-0-00754"]}],"id":[{"id":"10.13039\/501100008122","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,8,6]]},"DOI":"10.1109\/mwscas57524.2023.10405868","type":"proceedings-article","created":{"date-parts":[[2024,1,31]],"date-time":"2024-01-31T18:29:15Z","timestamp":1706725755000},"page":"212-216","source":"Crossref","is-referenced-by-count":6,"title":["Challenges on Design and Technology Co-Optimization: Design Automation Perspective"],"prefix":"10.1109","author":[{"given":"Taewhan","family":"Kim","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Seoul National University,South Korea"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2910579"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/iccad51958.2021.9643537"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2192477"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317868"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2019.2962782"},{"key":"ref7","article-title":"Spr: Smt-based simultaneous place-and-route for standard cell synthesis of advanced nodes","author":"Lee","year":"2020","journal-title":"TRRR TCAD"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/iccd53106.2021.00085"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2177459"},{"key":"ref10","article-title":"Allocation of multi-bit flip-flops in logic synthesis","volume-title":"IEEE\/ACM ICCAD","author":"Yi","year":"2016"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/12.55696"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2016.2597213"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3508352.3549351"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2852740"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353640"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898038"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3053223"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3036669.3036680"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2017.2731679"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643550"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3583781.3590278"},{"key":"ref22","volume-title":"Cadence innovus user guide"},{"key":"ref23","volume-title":"Opencore circuits"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510670"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137264"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2021.3066528"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3531437.3539712"}],"event":{"name":"2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)","location":"Tempe, AZ, USA","start":{"date-parts":[[2023,8,6]]},"end":{"date-parts":[[2023,8,9]]}},"container-title":["2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10405424\/10405847\/10405868.pdf?arnumber=10405868","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,2]],"date-time":"2024-02-02T00:10:28Z","timestamp":1706832628000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10405868\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,8,6]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/mwscas57524.2023.10405868","relation":{},"subject":[],"published":{"date-parts":[[2023,8,6]]}}}