{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:49:14Z","timestamp":1729619354997,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,10]]},"DOI":"10.1109\/nanoarch.2007.4400850","type":"proceedings-article","created":{"date-parts":[[2007,12,18]],"date-time":"2007-12-18T19:55:27Z","timestamp":1198007727000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["Dynamic redundancy allocation for reliable and high-performance nanocomputing"],"prefix":"10.1109","author":[{"family":"Shuo Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Lei Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Faquir Jain","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645806"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/92.661242"},{"key":"22","first-page":"373","article-title":"optimizing static job scheduling in a network of heterogeneous computers","author":"tang","year":"2001","journal-title":"International Conference on Parallel Processing"},{"key":"18","first-page":"58","article-title":"the expandable split window paradigm for exploiting fine-grain parallelism","author":"franklin","year":"1992","journal-title":"International Symposium on Microarchitecture"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237140"},{"key":"16","first-page":"141","article-title":"towards nanocomputer architecture","author":"beckett","year":"2002","journal-title":"Asia-Pacific Conference on Computer Systems Architecture"},{"key":"13","article-title":"limits of instruction-level parallelism","author":"wall","year":"1993","journal-title":"Wester Research Laboratory Research Report"},{"key":"14","doi-asserted-by":"crossref","first-page":"392","DOI":"10.1109\/ISCA.1995.524578","article-title":"Simultaneous multithreading: Maximizing on-chip parallelism","author":"tullsen","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.27"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676371"},{"key":"21","first-page":"402","article-title":"dynamic scheduling of parallel jos with qos demands in multiclusters and grids","author":"he","year":"2004","journal-title":"International Workshop on Grid Computing"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/4\/1\/004"},{"key":"20","first-page":"610","article-title":"performance evaluation of soft real-time scheduling on a multicomputer cluster","author":"zhu","year":"2000","journal-title":"International Conference on Distributed Computing Systems"},{"key":"2","doi-asserted-by":"crossref","first-page":"1313","DOI":"10.1126\/science.1066192","article-title":"logic gates and computation from assembled nanowire building blocks","volume":"294","author":"huang","year":"2001","journal-title":"Science"},{"key":"1","first-page":"94","article-title":"carbon nanotube field-effect transistors and logic circuits","author":"martel","year":"2002","journal-title":"IEEE Design Automation Conference"},{"key":"10","article-title":"probabilistic logics and the synthesis of reliable organisms from unreliable components","author":"von neumann","year":"1956","journal-title":"Automata Studies"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/92.285750"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/977091.977161"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/NANONET.2006.346223"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/5.663544"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/16\/6\/043"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2006.877431"}],"event":{"name":"2007 IEEE International Symposium on Nanoscale Architectures","start":{"date-parts":[[2007,10,21]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2007,10,22]]}},"container-title":["2007 IEEE International Symposium on Nanoscale Architectures"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4400848\/4400849\/04400850.pdf?arnumber=4400850","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,20]],"date-time":"2024-02-20T14:44:47Z","timestamp":1708440287000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4400850\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,10]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2007.4400850","relation":{},"subject":[],"published":{"date-parts":[[2007,10]]}}}