{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T12:29:06Z","timestamp":1725625746955},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,6]]},"DOI":"10.1109\/nanoarch.2010.5510923","type":"proceedings-article","created":{"date-parts":[[2010,7,23]],"date-time":"2010-07-23T09:50:59Z","timestamp":1279878659000},"page":"65-70","source":"Crossref","is-referenced-by-count":3,"title":["Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications"],"prefix":"10.1109","author":[{"given":"Michele","family":"De Marchi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. Haykel","family":"Ben Jamaa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"ref10","article-title":"Stanford University CNTFET Model"},{"year":"2009","key":"ref11","article-title":"Predictive Technology Model (PTM) for 32nm Bulk CMOS Technology Node"},{"key":"ref12","first-page":"70","article-title":"Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options For Living with Im-perfections","author":"deng","year":"2007","journal-title":"ISSCC 2007"},{"key":"ref13","first-page":"695","article-title":"A Neutral Netlist of 10 Combinational Benchmark Circuits","author":"brglez","year":"1985","journal-title":"ISCAS 1985"},{"year":"0","key":"ref14","article-title":"Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1063\/1.2171474"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.87.256805"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2009.5226348"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2007.4510963"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996624"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090742"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2004.1367820"},{"key":"ref1","first-page":"188","article-title":"Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates","author":"hu","year":"2007","journal-title":"Proc ICCAD"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/5.231340"}],"event":{"name":"2010 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)","start":{"date-parts":[[2010,6,17]]},"location":"Anaheim, CA, USA","end":{"date-parts":[[2010,6,18]]}},"container-title":["2010 IEEE\/ACM International Symposium on Nanoscale Architectures"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5506521\/5510921\/05510923.pdf?arnumber=5510923","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T15:52:26Z","timestamp":1489852346000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5510923\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,6]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2010.5510923","relation":{},"subject":[],"published":{"date-parts":[[2010,6]]}}}