{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:52:43Z","timestamp":1725551563352},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/nanoarch.2011.5941481","type":"proceedings-article","created":{"date-parts":[[2011,7,8]],"date-time":"2011-07-08T21:44:31Z","timestamp":1310161471000},"page":"37-44","source":"Crossref","is-referenced-by-count":4,"title":["Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop"],"prefix":"10.1109","author":[{"given":"Ramakrishnan","family":"Venkatasubramanian","sequence":"first","affiliation":[]},{"given":"Sujan K.","family":"Manohar","sequence":"additional","affiliation":[]},{"given":"Poras T.","family":"Balsara","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424383"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681660"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897161"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2252923"},{"key":"ref11","first-page":"363","article-title":"Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS","author":"calhoun","year":"0","journal-title":"Solid-State Circuits Conference 2005 ESSCIRC 2005 Proceedings of the 31st European"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0148"},{"key":"ref8","article-title":"High Efficiency Low Voltage DC-DC Conversion for Portable Applications in","author":"stratakos","year":"0","journal-title":"Chap 12"},{"year":"0","key":"ref7"},{"key":"ref2","article-title":"2009. Nanoelec-tromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage","author":"soogine","year":"0","journal-title":"In Proceedings of the 2009 International Conference on Computer-Aided Design (ICCAD ‘09)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845978"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074370"}],"event":{"name":"2011 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)","start":{"date-parts":[[2011,6,8]]},"location":"San Diego, CA, USA","end":{"date-parts":[[2011,6,9]]}},"container-title":["2011 IEEE\/ACM International Symposium on Nanoscale Architectures"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5934628\/5941474\/05941481.pdf?arnumber=5941481","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T06:10:39Z","timestamp":1490076639000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5941481\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2011.5941481","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}