{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T18:24:29Z","timestamp":1761675869830,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,6]]},"DOI":"10.1109\/nanoarch.2011.5941494","type":"proceedings-article","created":{"date-parts":[[2011,7,8]],"date-time":"2011-07-08T21:44:31Z","timestamp":1310161471000},"page":"129-136","source":"Crossref","is-referenced-by-count":57,"title":["Low-power functionality enhanced computation architecture using spin-based devices"],"prefix":"10.1109","author":[{"given":"Charles","family":"Augustine","sequence":"first","affiliation":[]},{"given":"Georgios","family":"Panagopoulos","sequence":"additional","affiliation":[]},{"given":"Behtash","family":"Behin-Aein","sequence":"additional","affiliation":[]},{"given":"Srikant","family":"Srinivasan","sequence":"additional","affiliation":[]},{"given":"Angik","family":"Sarkar","sequence":"additional","affiliation":[]},{"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2010.31"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"0","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1063\/1.3567772"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1038\/nphys1095"},{"journal-title":"Synopsys Design Compiler","year":"0","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.1962.16"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.48.7099"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.physrep.2006.01.001"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2025279"},{"key":"ref19","article-title":"All-Spin Logic Device with Intrinsic Non-Reciprocity","author":"srinivasan","year":"0","journal-title":"IEEE Trans Mag"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1063\/1.1368156"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1063\/1.122477"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283787"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1126\/science.1120506","article-title":"Majority Logic Gate for Magnetic Quantum-Dot Cellular Automata","volume":"311","author":"imre","year":"2006","journal-title":"Science"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703416"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2010.2079941"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2004.1263404"},{"key":"ref9","article-title":"Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective","author":"augustine","year":"2011","journal-title":"IEEE Sensors Journal"},{"article-title":"Leakage in Nanometer CMOS Technology","year":"2005","author":"narendra","key":"ref1"}],"event":{"name":"2011 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)","start":{"date-parts":[[2011,6,8]]},"location":"San Diego, CA, USA","end":{"date-parts":[[2011,6,9]]}},"container-title":["2011 IEEE\/ACM International Symposium on Nanoscale Architectures"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5934628\/5941474\/05941494.pdf?arnumber=5941494","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T03:00:07Z","timestamp":1497927607000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5941494\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2011.5941494","relation":{},"subject":[],"published":{"date-parts":[[2011,6]]}}}