{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:17:48Z","timestamp":1763468268339,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/nanoarch.2015.7180576","type":"proceedings-article","created":{"date-parts":[[2015,8,12]],"date-time":"2015-08-12T22:41:22Z","timestamp":1439419282000},"page":"7-12","source":"Crossref","is-referenced-by-count":3,"title":["An architecture-level cache simulation framework supporting advanced PMA STT-MRAM"],"prefix":"10.1109","author":[{"given":"Bi","family":"Wu","sequence":"first","affiliation":[]},{"given":"Yuanqing","family":"Cheng","sequence":"additional","affiliation":[]},{"given":"Ying","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Aida","family":"Todri-Sanial","sequence":"additional","affiliation":[]},{"given":"Guangyu","family":"Sun","sequence":"additional","affiliation":[]},{"given":"Lionel","family":"Torres","sequence":"additional","affiliation":[]},{"given":"Weisheng","family":"Zhao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"24.1.1","article-title":"Extended scalability of perpendicular STT-MRAM towards sub-20nm MTJ node","author":"kim","year":"2011","journal-title":"Proc of IEEE International Electron Devices Meeting (IEDM)"},{"key":"ref11","article-title":"DFSTT-MRAM: Dual Functional STT-MRAM Cell Structure for Reliability Enhancement and 3-D MLC Functionality","volume":"50","author":"kang","year":"2014","journal-title":"IEEE Transactions on Magnetics"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref13","article-title":"Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design","author":"zhang","year":"2014","journal-title":"Proc of IEEE International Solid-State and Integrated Circuit Technology (ICSICT)"},{"key":"ref14","first-page":"143","article-title":"Technology Comparison for Large Last-Level Caches (L3Cs): Low-Leakage SRAM, Low Write-Energy STT-RAM, and Refresh-Optimized eDRAM","author":"chang","year":"2013","journal-title":"Proc of IEEE International Symposium on High Performance Computer Architecture (HPCA)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6272069"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2014.07.019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2088143"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2009.2024325"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2024"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865703"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.actamat.2012.10.036"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"ref7","article-title":"CACTI 6.0: A tool to understand large caches","author":"muralimanohar","year":"2009","journal-title":"University of Utah and Hewlett Packard Laboratories Tech Rep"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.179"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703350"}],"event":{"name":"2015 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)","start":{"date-parts":[[2015,7,8]]},"location":"Boston, MA, USA","end":{"date-parts":[[2015,7,10]]}},"container-title":["Proceedings of the 2015 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH\u00b415)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7164206\/7180573\/07180576.pdf?arnumber=7180576","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T06:23:18Z","timestamp":1490422998000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7180576\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2015.7180576","relation":{},"subject":[],"published":{"date-parts":[[2015,7]]}}}