{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,23]],"date-time":"2026-01-23T22:56:23Z","timestamp":1769208983001,"version":"3.49.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/nanoarch.2015.7180592","type":"proceedings-article","created":{"date-parts":[[2015,8,12]],"date-time":"2015-08-12T22:41:22Z","timestamp":1439419282000},"page":"88-93","source":"Crossref","is-referenced-by-count":9,"title":["Fast march tests for defects in resistive memory"],"prefix":"10.1109","author":[{"given":"Seyed Nima","family":"Mozaffari","sequence":"first","affiliation":[]},{"given":"Spyros","family":"Tragoudas","sequence":"additional","affiliation":[]},{"given":"Themistoklis","family":"Haniotakis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818762"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2394434"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2004.75"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2215714"},{"key":"ref14","article-title":"Verilog-A for memristors models","author":"kvatinsky","year":"2011","journal-title":"CCIT Tech Rep 801"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/NAECON.2014.7045809"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2014.6850647"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.206"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050104"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1063\/1.3236506"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASQED.2010.5548311"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687491"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.66"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"250","DOI":"10.1109\/PEITS.2009.5407025","article-title":"An Optimal Control Strategy to alleviate sub-syncronous resonance in VSC-HVDC systems","volume":"1","author":"chehardeh","year":"2009","journal-title":"2nd International Conference on Power Electronics and Intelligent Transportation System (PEITS)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2013.219"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657045"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2013.2253329"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176603"},{"key":"ref22","article-title":"Bipolar OxPRAM Memory Array Reliability Evaluation based on Fault Injection","author":"aziza","year":"2011","journal-title":"Proc Design Test Workshop (IDT)"},{"key":"ref21","article-title":"Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits","author":"bushnell","year":"2000"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2010.5697869"}],"event":{"name":"2015 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)","location":"Boston, MA, USA","start":{"date-parts":[[2015,7,8]]},"end":{"date-parts":[[2015,7,10]]}},"container-title":["Proceedings of the 2015 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH\u00b415)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7164206\/7180573\/07180592.pdf?arnumber=7180592","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T17:31:48Z","timestamp":1498239108000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7180592\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2015.7180592","relation":{},"subject":[],"published":{"date-parts":[[2015,7]]}}}