{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T22:54:52Z","timestamp":1729637692603,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,7]]},"DOI":"10.1109\/nanoarch.2015.7180608","type":"proceedings-article","created":{"date-parts":[[2015,8,12]],"date-time":"2015-08-12T22:41:22Z","timestamp":1439419282000},"page":"175-180","source":"Crossref","is-referenced-by-count":6,"title":["Architecting connectivity for fine-grained 3-D vertically integrated circuits"],"prefix":"10.1109","author":[{"given":"Santosh","family":"Khasanvis","sequence":"first","affiliation":[]},{"given":"Mostafizur","family":"Rahman","sequence":"additional","affiliation":[]},{"given":"Mingyu","family":"Li","sequence":"additional","affiliation":[]},{"given":"Jiajun","family":"Shi","sequence":"additional","affiliation":[]},{"given":"Csaba Andras","family":"Moritz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"283","DOI":"10.1145\/2228360.2228414","article-title":"Exploring sub-20nm FinFET design with Predictive Technology Models","author":"sinha","year":"2012","journal-title":"Proceedings of 49th ACM\/EDAC\/ IEEE Design Automation Conference"},{"journal-title":"Interconnect_2011 Tables","year":"2012","key":"ref11"},{"journal-title":"PTM R-C Interconnect models","year":"2012","key":"ref12"},{"key":"ref13","article-title":"A stochastic wire-length distribution for gigascale integration (GSI)-Part II: Applications to clock frequency, power dissipation, and chip size estimation","volume":"45","author":"davis","year":"1998","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/92.902261"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"580","DOI":"10.1109\/16.661219","article-title":"a stochastic wire-length distribution for gigascale integration (gsi). i. derivation and validation","volume":"45","author":"davis","year":"1998","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/92.902258"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084635"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"122","DOI":"10.1145\/277044.277071","article-title":"Planning for performance","author":"otten","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"journal-title":"Circuits Interconnects and Packaging for VLSI","year":"1990","author":"bakoglu","key":"ref7"},{"article-title":"Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS","year":"0","author":"rahman","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.85"},{"journal-title":"PTM-MG device models for 16nm node","year":"2011","key":"ref9"}],"event":{"name":"2015 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH)","start":{"date-parts":[[2015,7,8]]},"location":"Boston, MA, USA","end":{"date-parts":[[2015,7,10]]}},"container-title":["Proceedings of the 2015 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH\u00b415)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7164206\/7180573\/07180608.pdf?arnumber=7180608","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,20]],"date-time":"2022-05-20T09:34:39Z","timestamp":1653039279000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7180608\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,7]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/nanoarch.2015.7180608","relation":{},"subject":[],"published":{"date-parts":[[2015,7]]}}}